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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
PM73123
AAL1GATOR-8
REFERENCE DESIGN
PRELIMINARY ISSUE 2: JUNE 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
PUBIC REVISION HISTORY Issue No. 1 2 Issue Date Details of Change December 1999 June 2001 Document created. Updated COMET-QUAD decoupling (C4, C6, C14, C21, C42, C49, C56, C65) in the schematics and corrected power sequencing description. Updated power calculations.
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
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CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 2 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATIONS ............................................................................ 1
GENERAL DESCRIPTION....................................................................... 3 2.1 AAL1GATOR-8 ARCHITECTURE ................................................. 3
3 4 5
FEATURES .............................................................................................. 6 HIGH LEVEL DESIGN ............................................................................. 7 BLOCK DESCRIPTION ......................................................................... 13 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 AAL1GATOR-8............................................................................ 13 COMET ....................................................................................... 15 COMET-QUAD ............................................................................ 17 THE MICROPROCESSOR INTERFACE BLOCK ....................... 18 AAL1GATOR-8 TO COMET/COMET-QUADS INTERCONNECTIONS ............................................................... 19 THE FPGA BLOCK ..................................................................... 20 AAL1GATOR-8'S SRAM ............................................................. 21 REGULATORS BLOCK............................................................... 21 LED BLOCKS.............................................................................. 21 RESET BLOCK ........................................................................... 22 JTAG PORT ................................................................................ 22 TIMING BLOCK........................................................................... 22 UTOPIA INTERFACE .................................................................. 23
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AAL1GATOR-8 REFERENCE DESIGN
6
DESIGN ISSUES ................................................................................... 24 6.1 AAL1GATOR-8 DESIGN CONSIDERATIONS ............................ 24 6.1.1 POWER SUPPLY ............................................................. 24 6.1.2 DECOUPLING .................................................................. 24 6.1.3 LINE MODE SELECTION................................................. 24 6.2 6.3 LINE TERMINATION ................................................................... 24 COMET DESIGN CONSIDERATIONS........................................ 24 6.3.1 POWER SUPPLY ............................................................. 24 6.3.2 DECOUPLING .................................................................. 25 6.3.3 VOLTAGE REFERENCES................................................ 25 6.4 COMET-QUAD DESIGN CONSIDERATIONS ............................ 25 6.4.1 POWER SUPPLY SEQUENCING .................................... 25 6.4.2 DECOUPLING .................................................................. 26 6.4.3 VOLTAGE REFERENCES................................................ 26 6.5 6.6 MICROPROCESSOR INTERFACE ............................................ 26 POWER REQUIREMENTS......................................................... 31
7
IMPLEMENTATION DESCRIPTION ...................................................... 33 7.1 7.2 AAL1GATOR-8 WITH COMET SCHEMATICS ........................... 33 AAL1GATOR-8 WITH COMET-QUAD SCHEMATICS ................ 35
8 9 10 11 12
GLOSSARY ........................................................................................... 37 DEFINITIONS ........................................................................................ 38 REFERENCES....................................................................................... 39 DISCLAIMER ......................................................................................... 40 APPENDIX A: BILL OF MATERIALS (COMET VERSION) .................... 41
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
13 14 15
APPENDIX B: BILL OF MATERIALS (COMET-QUAD VERSION)......... 43 APPENDIX C: AAL1GATOR-8 W/COMETS SCHEMATICS .................. 45 APPENDIX D: AAL1GATOR-8 W/COMET-QUADS SCHEMATICS....... 46
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
LIST OF FIGURES FIGURE 1 AAL1GATOR-8 CONFIGURATIONS ............................................... 3 FIGURE 2 AAL1GATOR-8 AND COMETS ........................................................ 4 FIGURE 3 AAL1GATOR-8 AND COMET-QUADS............................................. 5 FIGURE 4 AAL1GATOR-8 REF DESIGN BLOCK DIAGRAM WITH COMETS 8 FIGURE 5 AAL1GATOR-8 REF DESIGN DIAGRAM WITH COMET-QUADS .. 9 FIGURE 6 GLUELESS AAL1GATOR-8 TO COMETS CONNECTION.............11 FIGURE 7 GLUELESS AAL1GATOR-8 TO COMET-QUADS CONNECTION .11
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 AAL1GATOR-8 TO COMET/COMET-QUAD CONNECTIONS ...... 19 OSCILLATORS .............................................................................. 22 AAL1GATOR-8'S UTOPIA OPERATING MODES ......................... 23 INTERFACE PINOUT FOR AAL1GATOR-8 W/COMETS.............. 26 INTERFACE PINOUT FOR AAL1GATOR-8 W/COMET-QUADS... 28 ADDRESS SPACE FOR AAL1GATOR-8 W/COMETS .................. 30 ADDRESS SPACE FOR AAL1GATOR-8 W/COMET-QUADS ....... 30
TABLE 8 POWER CONSUMPTION FOR AAL1GATOR-8 W/COMETS .......... 31 TABLE 9 POWER FOR AAL1GATOR-8 W/COMET-QUADS ........................... 31 TABLE 10 MAJOR COMPONENTS LIST 1 .................................................... 41 TABLE 11 MAJOR COMPONENTS LIST 2 .................................................... 43
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
1
INTRODUCTION The AAL1gator-8 Reference Design assists customers in designing a Circuit Emulation Service (CES) and/or a Dynamic Bandwidth Circuit Emulation Service (DBCES) card. The CES/DBCES card is used to emulate circuit oriented transmission characteristics to support Constant Bit Rate (CBR) traffic.
1.1
PURPOSE This reference design will assist engineers in designing their products using PMC-Sierra's AAL1gator-8, COMET and COMET-QUAD devices thereby bringing customers' designs to market earlier.
1.2
SCOPE This document is a paper reference design and describes the scope and deliverables required for the AAL1gator-8 Reference Design. Note that the design was not actually built and tested, but has only been designed on paper. This reference design is a modularized card with two design options: 1. AAL1gator-8, two COMET-QUADs, a microprocessor interface, and line interfaces. 2. AAL1gator-8, eight COMETs, a microprocessor interface, and line interfaces. A block diagram is shown for the two designs. Descriptions are provided for each of the functional blocks and detailed implementation descriptions then follow.
1.3
APPLICATIONS Emulating existing TDM circuits is an essential function for ATM switches. Currently TDM circuits provide most voice and data services and therefore seamless interaction between TDM and ATM has become a system requirement. The ATM Forum has standardized an internetworking function that satisfies this requirement called the Circuit Emulation Services (CES) Specification. The following are some application examples of the AAL1gator-8 Reference Design: * An 8-Link T1/E1 CES Cards in a PBX
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AAL1GATOR-8 REFERENCE DESIGN
* *
TDM to ATM Access Service Concentrator Part of a TDM to ATM Multiservice ATM Switch
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AAL1GATOR-8 REFERENCE DESIGN
2 2.1
GENERAL DESCRIPTION AAL1gator-8 Architecture The purpose of the AAL1gator-8 is to provide high density T1/E1, or DS3/E3/J2 line interfaces access to an AAL1 CBR ATM network. The AAL1gator-8 can support 8 T1/E1 lines, 1 DS3/E3/STS-1 link or 2 8Mbps H-MVIP links. The AAL1gator-8 is capable of supporting 256 VCs. On the system side, the AAL1gator-8 supports a standard UTOPIA Level 2 interface that optionally supports parity and runs up to 52 MHz. An optional 8/16-bit Any-PHY slave interface and UTOPIA Level 1 master/slave interface are also supported on the system side. Figure 1 indicates the ways in which an AAL1gator-8 can be used to connect to T1/E1 or DS3/E3 line interfaces. Figure 1 AAL1gator-8 Configurations
Any-PHY / UTOPIA
AAL1gator-8
Structured or unstructured T1/E1 with CAS support MVIP TDM Switch Unstructured DS3/E3
T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer+LIU (COMET) or (COMET-Q)
DS3/E3 Framer (S/UNI-QJET)
T1/E1 LIU (QDSX)
M13 Mux (D3MX) DS3 LIU
DS3/E3 LIU
Figures 2 and 3 show the system context in which the AAL1gator-8 devices reside within the reference designs. In these designs each AAL1gator-8 can interface with eight COMETs or two COMET-QUADs to support 8 structured/unstructured T1s or E1s.
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
The PM4351 COMET is a single channel combined E1/T1 transceiver and framer, and the PM4354 COMET-QUAD is a four channel combined E1/T1 transceiver and framer - both devices are capable for use in long and short haul T1, J1 and E1 systems with a minimum of external circuitry. When used with the COMETs or COMET-QUADs, AAL1gator-8 can be part of a multiservice switch application which can provide circuit emulation services on E1 or T1 pipes. Figure 2 AAL1gator-8 and COMETs
Data and Clock Lines
Line Interface
PM4351 COMET
Line Interface
PM4351 COMET PM4351 COMET PM73123 AAL1gator-8
UTOPIA / AnyPHY
Line Interface
Line Interface
PM4351 COMET PM4351 COMET
Line Interface
Line Interface
PM4351 COMET PM4351 COMET
Line Interface
Line Interface
PM4351 COMET
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
Figure 3
AAL1gator-8 and COMET-QUADs
Data and Clock Lines
PM4354 COMET-QUAD
PM73123 AAL1gator-8
UTOPIA / AnyPHY
PM4354 COMET-QUAD
The COMETs or COMET-QUADs receive data through the T1/E1 line interfaces. The formatted data is then passed through the T1/E1 framers to the AAL1gator-8 for CBR servicing. The cells are then routed through a UTOPIA L2 connector for routing, switching, traffic policing and shaping. In the transmit path, the AAL1gator-8 receives the ATM cells from the UTOPIA bus. The AAL1gator-8 retrieves the data and signaling information, and places the data to be transmitted over the T1 or E1 lines via the COMETs or COMETQUADs in the appropriate port and time slot.
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
3
FEATURES * Implementation strategy for the AAL1gator-8 in a Multi Service Access Concentrator environment using the PM4351 COMET and PM4354 COMETQUAD. Supports 8 T1/E1 rates and channelized mode. Supports a CES. Supports independently clocked links. Has a microprocessor interface for configuration and monitoring.
* * * *
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
4
HIGH LEVEL DESIGN The block diagrams of the AAL1gator-8 reference design are shown in Figure 4 and Figure 5. Figure 4 illustrates the high level design of the reference design with 8 COMET devices while Figure 5 shows the high level design with two COMET-QUAD devices.
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
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AAL1GATOR-8 REFERENCE DESIGN
Figure 4
AAL1gator-8 Ref Design Block Diagram with COMETs
Microprocessor Interface Address Bus Control Bus
Reset Switch
Data Bus
2.5 V and 3.3 V Regulators
Memory system (Buffers/XCVRs, Decode Logic) Power LEDs
Address, Data and Control Bus Oscillators
RXRING1 & RXTIP1 TXRING1 &TXTIP1
PM4351 COMET
FPGA
RXRING2 & RXTIP2 TXRING2 &TXTIP2
PM4351 COMET
128Kx16 RAM PM4351 COMET
RXRING3 & RXTIP3 TXRING3 &TXTIP3
Data and clock Lines
RXRING4 & RXTIP4 TXRING4 &TXTIP4
PM4351 COMET
PM73123 AAL1gator-8
UTOPIA L2
UTIOPA L2 Connect
Line Interface
RXRING5 & RXTIP5 TXRING5 &TXTIP5
PM4351 COMET
RXRING6 & RXTIP6 TXRING6 &TXTIP6
PM4351 COMET
RXRING7 & RXTIP7 TXRING7 &TXTIP7
PM4351 COMET
AAL1gator-8 ALARM LEDs
RXRING8 & RXTIP8 TXRING8 &TXTIP8
PM4351 COMET
COMET ALARMS LEDs
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Figure 5
AAL1gator-8 Ref Design Diagram with COMET-QUADs
Microprocessor Interface Address Bus Control Bus Reset Switch
Data Bus
2.5 V and 3.3 V Regulators
Memory system (Buffers/XCVRs, Decode Logic) Power LEDs
Address, Data and Control Bus Oscillators
RXRING[4:1] RXTIP[4:1] TXTIP[4:1] TXRING[4:1] PM4354 COMET-QUAD FPGA 128Kx16 RAM
Line Interface
Data and clock Lines
PM73123 AAL1gator-8
UTOPIA L2
UTIOPA L2 Connect
TXRING[8:5] TXTIP[8:5] RXTIP[8:5] RXRING[8:5] PM4354 COMET-QUAD
COMET-QUAD ALARMS LEDs
AAL1gator-8 ALARM LEDs
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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
As illustrated, the designs contain the following functional blocks: 1. PM73123 AAL1gator-8 2. PM4351 COMET/PM4354 COMET-QUAD 3. Microprocessor and Memory System Interface 4. Field Programmable Gate Array (FPGA) 5. Line Interface 6. UTOPIA Interface 7. Power and Clock Sources The hardware allows full access to the AAL1gator-8 and COMET/COMET-QUAD devices via the microprocessor interface. Each COMET device acts as a single line interface unit with the integrated long haul LIU, and a T1/E1 framer/deframer while each COMET-QUAD device acts as four line interface units with the integrated long haul LIUs, and T1/E1 framers/de-framers. In the receive path (from a T1 or E1 line), a COMET or COMET-QUAD converts the incoming line data (in the form of channels) to a serial bit stream. The AAL1gator-8 then receives this data and clocking information and builds AAL1 cells to be sent to the UTOPIA bus. In the transmit path (to a T1 or E1 line), the AAL1gator-8 receives the ATM cells from the UTOPIA bus. The AAL1gator-8 retrieves the data and signaling information, and places the data to be transmitted over the T1 or E1 lines via the COMETs/COMET-QUADs in the appropriate port and time slot. As illustrated in both Figure 4 and Figure 5, the connections from the FPGA to the PMC's devices are dotted lines. This is because it is possible to connect the AAL1gator-8 to the COMETs or COMET-QUADs directly (i.e. without using a FPGA). Figure 6 shows the direct connection between the AAL1gator-8 and COMETs while Figure 7 illustrates this glueless interconnection between AAL1gator-8 and COMET-QUADs.
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Figure 6
Glueless AAL1gator-8 to COMETs Connection
Optional External Clock Source
BTCLK[7..0] BTSIG[7..0]
TL_CLK[7..0] TL_SIG[7..0]
8 COMET Blocks
BTFP[7..0]
PM73123 AAL1gator-8
TL_SYNC[7..0]
Figure 7
Glueless AAL1gator-8 to COMET-QUADs Connection
Optional External Clock Source
BTCLK[4..1] BTSIG[4..1]
PM4354 COMET-QUAD
TL_CLK[7..0] TL_SIG[7..0]
BTFP[4..1]
PM73123 AAL1gator-8
BTFP[4..1] TL_SYNC[7..0]
PM4354 COMET-QUAD
BTSIG[4..1] BTCLK[4..1]
The AAL1gator-8 also supports 8Mbit/s H-MVIP on the line interface, and the COMET-QUAD also supports 8Mbit/s H-MVIP on the system interface.
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AAL1GATOR-8 REFERENCE DESIGN
Therefore, an H-MVIP interface is optionally provided for the AAL1gator-8 with COMET-QUAD Reference design. The main purpose of the FPGA is to provide maximum clock distribution flexibility by allowing for independently clocked links. The AAL1gator-8 is capable of implementing SRTS and the Adaptive Clock Recovery algorithm on its own; however, using an FPGA it is possible to implement an external Adaptive Clock Recovery scheme or SRTS clock scheme. The FPGA is also used for the generation of TL_CLK (AAL1gator-8) and BTCLK (COMET and COMET-QUAD). In addition, the FPGA generates an appropriate signal for the AAL1gator-8 network clock pin, N_CLK, (at 2.43 MHz), and also distributes XCLK signals to the 8 COMET or two COMET-QUAD devices from only two clock oscillators: 1.544 MHz and 2.048 MHz. In H-MVIP mode, the FPGA is used to distribute the 16.384 MHz clock to the AAL1gator-8's C16B and to the COMET-QUADs' CMV8MCLK input pins. The FPGA is also used to distribute the 4.096 MHz Frame Pulse Clock to the AAL1gator-8's C4B and to the COMET-QUADs' CMVPFC inputs, and to generate the 8 kHz Common H-MVIP Frame Pulse from the Frame Pulse Clock. In addition, in both Figures 6 and 7, the TL_SYNC pins of the AAL1gator-8 are connected to the COMET BTFP pin or the COMET-QUAD BTFP pins (configured as outputs). Depending on the value of MF_SYNC_MODE in the LI_CFG_REG register of the AAL1gator-8 for the line, this allows for alignment of signaling bits on multiframe boundaries or a frame boundary. Power requirements of the boards are +5.0V, +3.3V and +2.5V. The AAL1gator8 and COMET-QUADs require +3.3V and +2.5V while COMETs require only +3.3V. +5.0V is used as input to the COMETs' BIAS pins and to generate the +3.3V and +2.5V using voltage regulators. In this reference design, the AAL1gator-8, COMET and COMET-QUAD devices are configured with de-multiplexed microprocessor address and data bus. The microprocessor interface has been provided through a 96-pin connector. This interface provides configuration and monitoring for PMC-Sierra's devices. The memory sub-unit of the AAL1gator-8's block contains a 128k x 16 SRAM module connected to the AAL1gator-8 device's RAM interface. Two 80-pin female UTOPIA connectors carry the receive and transmit UTOPIA signals between the AAL1gator-8 and an external PHY board or a Parallel Cell Traffic Generator and Analyzer. The designs also include several LED circuits for the device alarms and power indications.
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5 5.1
BLOCK DESCRIPTION AAL1gator-8 The AAL1 Segmentation and Reassembly (SAR) Processor (AAL1gator-8) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external (128K x 16/18 bits) 10ns SRAM for storage of the configuration, the user data, and the statistics. Some of the device's important functionality is as follows: * * * * * * Compliant with the ATM Forum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum's DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. Provides AAL1 segmentation and reassembly of 8 individual E1 or T1 lines, 2 H-MVIP lines at 8Mbit/s, or 1 E3 or DS3 line. Provides a standard 16/8 bits UTOPIA level 2 Interface which optionally supports parity and runs up to 50 MHz. The following modes are supported: * * * * * 16-bit Level 2, Multi-Phy Mode (MPHY) 8-bit Level 2, MPHY 8-bit Level 1, SPHY 8-bit Level 1, ATM Master
Supports up to 256 Virtual Channels (VC).
The AAL1gator-8 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.
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In this reference design, the AAL1gator-8 is configured with the direct mode at the line interface to connect to 8 COMETs or 2 COMET-QUADs. The line mode of operation needs to be setup from hardware reset and cannot be changed once the chip is powered up. The line mode is controlled by the AAL1gator-8's LINE_MODE pin. When the LINE_MODE pin is set to low using the provided jumpers the AAL1gator-8 will support 8 low speed lines, or one high speed line, to interface with the COMET or COMET-QUAD devices. When the LINE_MODE pin is set to high, the AAL1gator-8 will be in H-MVIP mode when interfacing to the COMET-QUADs. This mode is provided as an extra and optional interface and can be ignored. The UTOPIA interface of the AAL1gator-8 will power up with all outputs tri-stated and will remain tri-stated until the UI_EN bit in the UI_COMN_CFG register is set. Also, during the hardware configuration of the AAL1gator-8, the TL_CLK_OE signal is tied high to use the clock provided on its RL_CLK pin as its TL_CLK and will drive this clock externally. When the chip is taken out of hardware reset, the internal DLL on SYSCLK, which used to maintain low skew on the RAM interface, will go into hunt mode and will adjust the internal SYSCLK until it aligns with the external SYSCLK. The microprocessor should poll the RUN bit in the DLL_STAT_REG register until this bit is set. At this point, the entire chip with the exception of the microprocessor interface and the DLL are in reset. Before any configuration can be done, including accessing the RAM, the chip must be taken out of software reset by clearing the SW_RESET bit in the DEV_ID_REG register. Then, the RAM should be cleared to all zeros. At this point, the A1SP block is still in reset because its SW_RESET bit in the CMD_REG register is still set. The line interface is configured in the direct low speed mode indicated by the LINE_MODE pins but all internal registers are in the reset state. The line interface is out of reset at this point but will only be driving data as if all lines and/or queues are disabled. The UTOPIA interface, as mentioned above, is disabled and all UTOPIA outputs are tri-stated. The software configuration of the AAL1gator-8 is done in three steps: 1. Line Configuration: while the A1SP is in reset, the memory mapped registers which contain the line configuration (the LIN_STR_MODE and HS_LIN_REG registers) can be initialized. Then, the CMD_ATTN bit in the CMD_REG register can be set so that the A1SP can read its configuration. The SW_RESET bit of the CMD_REG register should remain set. 2. Queue Configuration: the SW_RESET bit in the CMD_REG register is cleared which takes A1SP out of reset. The R_CHAN_2_QUE_TBL will then
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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
begin a 640 SYSCLK cycle initialization, which reset each timeslot to playing out conditioned data. At this point, the queues can be initialized as needed. 3. Adding Queues: By setting the corresponding bits in the ADDQ_FIFO register, the queues are added. For a more detailed description of the AAL1gator-8, please refer to [1]. 5.2 COMET The PM4351 Combined E1/T1 Transceiver (COMET) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1 and E1 systems with a minimum of external circuitry. The COMET is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024MHz in E1 mode) or up to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digital line inputs are provided for applications not requiring a physical T1 or E1 interface. The COMET recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to several DS-1 signal formats: SF, ESF, T1DM (DDS) and SLC(R)96. In E1 mode, the COMET frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. In T1 mode, the COMET generates framing for SF, ESF and T1DM (DDS) formats. In E1 mode, the COMET generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Digital line inputs and outputs are provided for applications not requiring a physical T1 or E1 interface.
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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
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The COMET provides both a parallel microprocessor interface for controlling the operation of the device and serial PCM interfaces that allow backplane rates from 1.544 Mbit/s to 8.192 Mbit/s to be directly supported. In this reference design, each COMET interfaces with the AAL1gator-8 can be configured independently in T1 or E1 mode. After the power up or a hardware/software reset, the following steps are performed to configure the COMET: 1. Initialize the XLPG (Transmit Pulse Template) registers to clear the pulse template. 2. Setup the XLPG to program the pulse template to generate short-haul or long-haul pulses as specified in [2]. Also, set the amplitude of the pulse template and enable the XLPG. 3. Program the COMET for T1 or E1 mode by writing to the E1/T1B bit of the Global Configuration register. 4. Configure the Clock Synthesis Unit (CSU) by selecting 1.544MHz or 2.048MHz for the line rate (XCLK and TCLKO). 5. Configure the Clock and Data Recovery Unit (CDRC) to receive the appropriate line decoding (AMI or B8ZS in T1 mode, HDB3 in E1 mode). 6. Configure the Receive and Transmit Elastic Stores units (RX-ELST and TXELST). 7. Set the framing format and line encoding for the transmitter (XBAS in T1 mode, E1-TRAN in E1 mode). 8. Program the framing format for the receiver. 9. Configure the framing format and the data rate for the facility data link. 10. Configure the Signaling Extraction Block register (SIGX). 11. Configure the Receive Line Interface (RLPS). 12. Configure the Transmit/Receive Jitter Attenuator and the Receive Option registers to disable or enable the jitter attenuation on transmit or receive line side. 13. Configure the Backplane Receive System Interface (BRIF) block (registers 0x30 and 0x31):
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* * * * *
Full Frame mode BRCLK as an output BRPCM, BRSIG, and BRFP updated on the rising edge of BRCLK BRCLK backplane rate (1.544MHz or 2.048MHz) BRFP (Backplane Frame Pulse) as an output
14. Configure the Backplane Transmit System Interface (BTIF) block (registers 0x40 and 0x41): * * * * * Full Frame mode BRCLK as an input BTPCM, BTSIG, and BTFP updated on the rising edge of BTCLK BTCLK backplane rate (1.544MHz or 2.048MHz) BRFP (Backplane Frame Pulse) as an output
15. Program the Receive Line Equalization table as stated in [2]. For more information about the COMET please refer to [2]. 5.3 COMET-QUAD The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1
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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
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mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. In synchronous backplane systems 8Mbit/s H-MVIP interfaces are provided for access channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The DS0 data channel H-MVIP and CAS H-MVIP access is multiplexed with the serial PCM interface pins. The CCS signaling HMVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1/E1 slip buffers. The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. Please refer to [3] for more information about the COMET-QUAD. 5.4 The Microprocessor Interface Block The microprocessor interface contains de-multiplexed address and data buses and a control bus to perform the following functions on the AAL1gator-8 Reference Design:
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* *
Configuration of the AAL1gator-8 and COMET or COMET-QUAD devices Monitoring of alarms and interrupts in the AAL1gator-8 and COMET or COMET-QUAD devices
In order to provide maximum system implementation flexibility, a particular microprocessor has not been specified. However, the system microprocessor must have the following minimum capabilities: 1. 2. 3. 4. 23 bit address bus 6 bit data bus 3 programmable chip selects 2 independent interrupt request lines
An example of a microprocessor that meets these minimum requirements is the Motorola MC68340. Another option would be to implement the design in a PCI or compact PCI system. 5.5 AAL1gator-8 to COMET/COMET-QUADs Interconnections The AAL1gator-8 communicates with the COMET/COMET-QUAD devices via framer bus signals listed in Table 1. Four bits of each signal group connects to one COMET-QUAD device. For instance, TL_SYNC[3..0] are connected to the COMET-QUAD 1, while TL_SYNC[7..4] are connected to COMET-QUAD 2. Table 1 SIGNAL TL_SYNC[7..0] TL_CLK[7..0] RL_CLK[7..0] RL_SYNC[7..0] RL_SIG[7..0] RL_DATA[7..0] TL_SIG[7..0] TL_DATA[7..0] AAL1gator-8 to COMET/COMET-QUAD Connections DESCRIPTION The FPGA generates this signal for both the AAL1gator-8 and COMET/COMET-QUADs. In T1 mode, this signal consists of a pulse once every 193 bit periods. This is a clock signal at the transmit line rate. Its source is determined by the configuration of the FPGA. Receive line clock at either 1.544 MHz or 2.048 MHz, derived from the recovered line rate timing. Carries receive frame synchronization from the COMET/COMETQUAD devices. Carries the CAS signaling information from the COMET/COMETQUAD devices. Carries the receive data from the COMET/COMET-QUAD devices. Carries the CAS signaling outputs to the COMET/COMET-QUAD devices. Carries the serial data to the COMET/COMET-QUAD devices.
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5.6
The FPGA Block If the direct connections between the AAL1gator-8 and the COMETs or the COMET-QUADs are not used, depending upon the configuration, the Field Programmable Gate Array (FPGA) performs the following optional functions: 1. Implements an external Adaptive Clock Recovery scheme if a designer would like to perform an external algorithm instead of the AAL1gator-8's own internal algorithm. 2. Distributes XCLK source among the COMET or COMET-QUAD devices. 3. Generates the 8 kHz framing pulses. 4. Generates a software selected N_CLK signal (2.43 MHz) from the Network clock. Note that the AAL1gator-8 is capable of implementing SRTS or Adaptive Clock Recovery scheme on its own; therefore, the FPGA is not required to perform these methods, but it is required to perform the other functions as mentioned in items 2-4 above. In the adaptive Clock recovery mode, the AAL1gator-8 provides a queue depth difference for controlling of an external clock. The FPGA latches the channel status and frame difference and uses them to adjust the synthesized clock frequency. If the queue depth is low, the clock frequency is reduced; however, if the queue depth is high, the clock frequency is increased. The FPGA also distributes XCLK signals to the 8 COMET or two COMET-QUAD devices from only two clock oscillators: 1.544 MHz and 2.048 MHz. Another function of the FPGA is to generate the 8 kHz framing pulse from the transmit line clock (BTCLK in the COMET or in the COMET-QUAD) to the framers. This 8 kHz signal connects to the AAL1gator-8 TL_SYNC input and the COMET's or COMET-QUAD's BTFP input. In the T1 mode, the frame pulse (BTFP) is one clock (BTCLK) period wide, generated every 193 bits. But, in the E1 mode, the frame pulse is generated every 256 bits. For implementation of the synchronous residual time stamp (SRTS), the AAL1gator-8's network clock (N_CLK) must be a 2.43 MHz signal. This signal is generated by dividing a 155.52 MHz ATM network clock by 64 in the FPGA. In the AAL1gator-8 with COMET-QUADs Reference Design, if the H-MVIP mode is used, the FPGA is used to distribute the 16.384 MHz clock to the AAL1gator8's C16B and to the COMET-QUADs' CMV8MCLK input pins. The FPGA is also used to distribute the 4.096 MHz Frame Pulse Clock to the AAL1gator-8's C4B
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and to the COMET-QUADs' CMVPFC inputs, and to generate the 8 kHz Common H-MVIP Frame Pulse from the Frame Pulse Clock. The H-MVIP common frame pulse is sampled on the falling edge of the 4.096 MHz clock and occurs every 125us (i.e. occurs every 512 pulse). 5.7 AAL1gator-8's SRAM A 128k x 16 bit pipelined SRAM or ZBT RAM can be used to interface with AAL1gator-8. In this reference design, a pipelined Synchronous NBT (No Bus Turn Around) SRAM, GS841Z18, from GSI Technology is used due to low power consumption (of approximately 100 mA at 3.3V less than other vendors). The GS841Z18 SRAM (256k x 18) has 18 bi-directional data pins two of which indicate odd parity for the lower and upper bytes of data. Note that since there is not any 128k x 16-bit ZBT SRAMs in the market, a 256k x 16-bit ZBT SRAM is used for this reference design. Other manufacturers such as Cypress Semiconductor's NoBL, Samsung Electronics' NtRAM, or Integrated Device Technology's ZBT RAMS can also be used instead of the GS841Z8 NBT SRAM due to the pin compatibility. 5.8 Regulators Block To generate +3.3V and +2.5V voltages from +5V (Vcc), two low drop out voltage regulators: LT1528 and LT1118CST are used in the AAL1gator-8 Reference Design. The LT1528 voltage regulator provides up to 3A at 3.3V to the board. The LT1118CST voltage regulator provides up to 0.500A at 2.5V to the AAL1gator-8 with COMETs reference design and up to 0.750A at 2.5 V to the AAL1gator-8 with COMET-QUADs reference design. Both regulators should be in the DD package, so that no additional heat sink is required. The dissipated heat for each regulator is: P = (5 - 3.3) V x 3.0 A = 5.1 W for LT1528 P = (5 - 2.5) V x 0.5 A = 1.25 W for LT1118CST in AAL1gator-8 w/COMETs P = (5 - 2.5) V x 0.75 A = 1.875 W for LT1118CST in AAL1gator-8 w/COMET-Q 5.9 LED Blocks The LED blocks contain super green and yellow LEDs. The 3 super green LEDs are used to show power status of +5V, +3.3V and +2.5V power sources.
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The yellow LEDs are used for interrupt and alarm monitoring the AAL1gator-8, COMET and COMET-QUAD devices. 5.10 RESET Block The hardware reset circuitry is constructed with a pushbutton switch and the MAX700 Power-Supply Monitor with Reset device circuitry. 5.11 JTAG Port The JTAG port is connected among all devices to allow for boundary scan testing. The signals are connected in the following way: * * * TMS The Test Mode Select signal is connected in parallel among all COMET/COMET-QUAD devices, NBT SRAM and the AAL1gator-8. TCK The Test Clock signal is connected in parallel among all COMET/COMET-QUAD devices, NBT SRAM and the AAL1gator-8. TRSTB The Test Reset Select signal is connected in parallel among all COMET/COMET-QUAD devices and the AAL1gator-8. The source of this signal may either be the JTAG controller, or from a pushbutton activation TDI/TDO The Test Data Input/Test Data Output signal is connected serially among all COMET/COMET-QUAD devices, NBT SRAM and the AAL1gator-8, beginning with the AAL1gator-8, and ending with the last COMET/COMETQUAD device.
*
The JTAG port signals connect to an externally accessible header. 5.12 Timing Block The timing block consists of the oscillators and part of the FPGA. The 50ppm HCMOS oscillators chosen are packaged in half-sized metal can DIP. Table 2 shows the type and functionality of the oscillators used in the reference design. Table 2 Frequency (MHz) 1.544 2.048 Oscillators PPM 50 50 Usage Provides XCLK signals to the COMETs or COMETQUADs in T1 mode. Provides XCLK signals to the COMETs or COMET-
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QUADs in E1 mode. 38.88 50 Provides the AAL1gator-8's system clock (AAL1_SYSCLK) and the AAL1gator-8's SRAM clock (RAM_CLK) Used in H-MVIP mode to generate and sample the HMVIP frame pulse signal. Used in H-MVIP mode to provide the common clock used to transfer data across the H-MVIP bus.
4.096 16.384 5.13
50 50
UTOPIA Interface The AAL1gator-8 can communicate with any ATM layer devices (such as the S/UNI-ATLAS) via the UTOPIA interface. Please refer to UTOPIA Interface signals in the AAL1gator-8 data sheet [1] for description of the individual signals. There are two possible bus modes of operation for the AAL1gator-8: UTOPIA mode and Any-PHY mode. These configurations are possible through the AAL1gator-8's UI_Source_Config Register (UI_SRC_CFG). When the ANY_PHY_EN bit in this register is cleared (ANY_PHY_EN = `0'), the AAL1gator8 is configured with a UTOPIA interface. When the ANY_PHY_EN bit is set (ANY_PHY_EN = `1'), the device is in the Any-PHY mode. Also, the UTOP_MODE [1:0] bits in this register selects the UTOPIA operating mode for the source side interface as illustrated in Table 3. Table 3 AAL1gator-8's UTOPIA Operating Modes Operating Mode UTOPIA-Level 1 Master UTOPIA-Level 1 Slave UTOPIA-Level 2 Single Address Slave Reserved
UTOP_MODE[1:0] `00' `01' `10' `11'
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6 6.1
DESIGN ISSUES AAL1gator-8 Design Considerations
6.1.1 Power Supply The power to the +3.3V pins should be applied before power to +2.5V pins is applied. All the ground pins (PPL, PQL, and PCL) should be connected together. 6.1.2 Decoupling A 0.01F capacitor is placed between power and ground for the +2.5V and +3.3Vpins. The capacitors should be placed as close to the actual pin as possible. 6.1.3 Line Mode Selection The AAL1gator-8 can be configured to operate in direct mode by setting the Line_Mode pin low or high for H-MVIP mode. For this purpose a set of jumpers are provided to select ground (low) or +3.3V. (high). This hardware configuration must be done prior to power up. 6.2 Line Termination For each of the 8 line terminations to the COMET or COMET-QUAD devices, this reference design uses a termination that compromises between 100 Ohm T1 and 120 Ohm E1. The 75 Ohm E1 termination has not been used. 6.3 COMET Design Considerations
6.3.1 Power Supply During power-up, the BIAS pin must be equal to or greater than the voltage on the VDD pins. This is accomplished with the voltage regulator. The voltage on the BIAS pin is also the same one used to regulate the VDD voltage. Therefore, the worst case is that the regulator malfunctions and shorts, which still leaves the BIAS pin equal to VDD. Also, an extra protection diode is used to limit the VDD to a maximum of 0.5V above the BIAS voltage. Analog power pins must be applied after VDD or they must be current limited to the maximum latch-up current of 100mA. A simple solution is to use a small filtering network between the VDD and AVD pins to delay the power.
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The differential voltage measured between AVD supplies and VDD must be less than 0.5V. 6.3.2 Decoupling A 0.01F capacitor is placed between power and ground for the VDDO pins. A 0.1F capacitor is placed between power and ground for the VDDI pins. The capacitors should be placed as close to the actual pin as possible. The AVD pins require a filtering network between the VDD plane and each AVD pin. The network is a single RC network with the resistor between the VDD plane and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics in Appendix A for component values. 6.3.3 Voltage References The Transmit Voltage Reference pin (TVREF) requires a 4.7uF capacitor to analog ground and two 12.7Ohm resistors to the corresponding TxRING and TxTIP pins. The Reference Voltage Reference pin (RVREF), which is reserved for a precision analog voltage or current reference, must be connected to a RC circuit consisting of a 100 kohm resistor connected in parallel with a 10nF capacitor to analog ground. 6.4 COMET-QUAD Design Considerations
6.4.1 Power Supply Sequencing The following power up sequence for the COMET-QUAD must be followed: 1. 2. 3. +3.3V digital pins +3.3V analog pins (TAVDx, CAVD, RAVDx, QAVD) +2.5V digital pins
Power to the +3.3V pins, both analog and digital, must be applied before +2.5V. Power to the +3.3V digital pins must be applied before power to the +3.3V analog. A simple solution for the latter statement is to use a small filtering network between the +3.3V digital and +3.3V analog pins to delay the power.
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6.4.2 Decoupling 0.01F and 0.1F capacitors are placed between power and ground for the VDD (+2.5 V and +3.3V) pins. The capacitors should be placed as close to the actual pins as possible. The AVD pins require a filtering network between the VDD plane and each AVD pin. The network is a single RC network with the resistor between the VDD plane and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics in Appendix A for component values. 6.4.3 Voltage References Each of The Transmit Common Mode pin (TxCM[1:4]) requires 4.7uF capacitors to analog ground and two 12.7Ohm resistors to the corresponding TxRING and TxTIP pins. The Reference Voltage Reference pin (RVREF), which is reserved for a precision analog voltage or current reference, must be connected to a RC circuit consisting of a 100 kohm resistor connected in parallel with a 10nF capacitor to analog ground. 6.5 Microprocessor Interface Table 4 and Table 5 list the pin assignment of potential microprocessor interfaces (96 pin DIN) for AAL1gator-8 reference design with COMETs and COMETQUADs, respectively. Note that these interfaces include all connections from the microprocessor to the AAL1gator-8, COMET and COMET-QUAD devices, and FPGA. Table 4 PIN NAME UP_D(15) UP_D(14) UP_D(13) UP_D(12) UP_D(11) UP_D(10) UP_D(9) UP_D(8) UP_D(7) UP_D(6) Interface Pinout for AAL1gator-8 w/COMETs PIN TYPE I/O PIN NUMBER A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 FUNCTION 16 bit data bus
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PIN NAME UP_D(5) UP_D(4) UP_D(3) UP_D(2) UP_D(1) UP_D(0) UP_A(23) UP_A(22) UP_A(21) UP_A(20) UP_A(19) UP_A(18) UP_A(17) UP_A(16) UP_A(15) UP_A(14) UP_A(13) UP_A(12) UP_A(11) UP_A(10) UP_A(9) UP_A(8) UP_A(7) UP_A(6) UP_A(5) UP_A(4) UP_A(3) UP_A(2) UP_A(1) UP_A(0) RDB_IN WRB_IN AAL1_ACKB AAL1_INTB IRQ2B RSTB AAL1_CSB
PIN TYPE
Input (from uP)
Input Input Input Output (to uP) Output Input Input
PIN NUMBER A27 A28 A29 A30 A31 A32 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C7 C8 C1 C5 C7 A1 C2
FUNCTION
24 bit address bus
Active Low read signal Active Low write signal. Active Low acknowledge signal to uP. Active low interrupt request to uP. from AAL1gator-8 Active low interrupt request to uP from Framer Active low global reset. Active low chip select. When asserted, the AAL1gator-8 is selected.
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PIN NAME CS2B CS3B GND Table 5 PIN NAME UP_D(15) UP_D(14) UP_D(13) UP_D(12) UP_D(11) UP_D(10) UP_D(9) UP_D(8) UP_D(7) UP_D(6) UP_D(5) UP_D(4) UP_D(3) UP_D(2) UP_D(1) UP_D(0) UP_A(21) UP_A(20) UP_A(19) UP_A(18) UP_A(17) UP_A(16) UP_A(15) UP_A(14) UP_A(13) UP_A(12) UP_A(11) UP_A(10) UP_A(9) UP_A(8) UP_A(7) UP_A(6) UP_A(5)
PIN TYPE Input Input n/a
PIN NUMBER C3 C4 B1 - B26
FUNCTION Active low chip select. When asserted the COMET is selected. Active low chip select. When asserted, the FPGA is selected. GND. Ground Reference
Interface Pinout for AAL1gator-8 w/COMET-QUADs PIN TYPE I/O PIN NUMBER A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 FUNCTION 16 bit data bus
Input (from uP)
22bit address bus
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PIN NAME UP_A(4) UP_A(3) UP_A(2) UP_A(1) UP_A(0) RDB_IN WRB_IN AAL1_ACKB AAL1_INTB IRQ2B RSTB AAL1_CSB CS2B CS3B GND
PIN TYPE
Input Input Input Output (to uP) Output Input Input Input Input n/a
PIN NUMBER C28 C29 C30 C31 C32 C7 C8 C1 C5 C7 A1 C2 C3 C4 B1 - B26
FUNCTION
Active Low read signal Active Low write signal. Active Low acknowledge signal to uP. Active low interrupt request to uP. from AAL1gator-8 Active low interrupt request to uP from Framer Active low global reset. Active low chip select. When asserted, the AAL1gator-8 is selected. Active low chip select. When asserted, the COMET-QUAD is selected. Active low chip select. When asserted, the FPGA is selected. GND. Ground Reference
Figures 4 and 5 indicate the usage of external address buffers and data transceivers. In order for the system to operate at the maximum frequency of 40.00 MHz, the address buffers must have a worst case propagation delay of 8ns, while the data transceivers must have a worst case delay of 10ns. For these reasons the IDT74FCT163827CT was chosen as the address buffer. This 20 bit device has a maximum propagation delay of 4.4ns (50pF, 500 load). The IDT74FCT163646 was chosen as the data transceiver. This 16-bit device has a worst case propagation delay of 5.4ns under the same loading conditions. When the microprocessor wishes to communicate with a COMET device, it asserts an address as listed in the Table 6. When an appropriate address is driven onto the bus, the microprocessor simultaneously asserts CS2B. Since A23 is high, the decoder is then active. Address bits A[22..20] determine which output of the decoder is driven low. One decoder output connects to the CSB input of each COMET device. For example, if A[22..20] are 000, then decoder output Y0 is driven low, which also asserts CSB of COMET0. No other COMET
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device is selected at this time. Address bits A[8..0] determine which register of the COMET the microprocessor is communicating with. In order to meet the timing requirements of the COMET devices (refer to [2]), the 3-8 decoder (74HCT138) must have a maximum propagation delay of 10ns. With a 15pF load, the device has a typical delay of 13ns. At 50pf (VCC = 4.5), the delay increases to 38ns, and therefore will meet the specifications. Table 6 Address Space for AAL1gator-8 w/COMETs BASE ADDRESS 000000h 800000h 900000h A00000h B00000h C00000h D00000h E00000h F00000h ADDRESS RANGE 000000 - 0FFFFFh 800000 - 8001FFh 900000 - 9001FFh A00000 - A001FFh B00000 - B001FFh C00000 - C001FFh D00000 - D001FFh E00000 - E001FFh F00000 - F001FFh
DEVICE AAL1gator-8 COMET0 COMET1 COMET2 COMET3 COMET4 COMET5 COMET6 COMET7
Table 7 shows the Address ranges of the devices used in the AAL1gator-8 with COMET-QUADs reference design. Table 7 Address Space for AAL1gator-8 w/COMET-QUADs BASE ADDRESS 000000h 200000h 300000h ADDRESS RANGE 000000 - 0FFFFFh 200000 - 2007FFh 300000 - 3007FFh
DEVICE AAL1gator-8 COMET-QUAD0 COMET-QUAD1
Since the address and data buses are shared among many devices, a 20 bit buffer and transceiver is used. This insures that clean signals are present on the inputs of the devices, and that no data collisions occur. The buffer (FCT163827) is not only placed on the address lines, but the various control signals such as WRB and RDB as well. The 16-bit transceiver (FCT163646) is used in flow through mode to control data bus access. The transceivers output enable is controlled by the result of a logical AND of CS2B and CS3B. In this way, whenever the microprocessor needs to communicate with either a COMET/COMET-QUAD or the FPGA, either the CS2B, or CS3B signal must be driven low, which drives the active low output enable signal of the transceiver low. The transceivers' direction is controlled by the WRB signal.
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6.6
Power Requirements Table 8 provides the estimated power requirements for the AAL1gator-8 Reference Design with COMETs. Table 9 for AAL1gator-8 w/COMET-QUADs provides the maximum power requirements for the AAL1gator-8 Reference Design with COMET-QUADs. Table 8 Power Consumption for AAL1gator-8 w/COMETs
5V Components 74HCT138A (SOIC) LEDs 74HCT08 Misc, pullups/downs Total 5V Power 3.3V Components COMET AAL1gator-8 FPGA GSI NBT SRAM Oscillators LEDs Buffers/Transceivers Misc. Total 3.3V Power 2.5V Components AAL1gator-8 Total 2.5V Power
Quantity Current (mA) Power (mW)
1 3 1 1
100 15 3 100
500 225 15 500 1240 (mW)
Power (mW)
Quantity
Current (mA)
8 1 1 1 5 8 4 1
250 122 360 210 40 20 5.5 200
6600 402.6 1188 693 660 528 72.6 660 10804.(mW)
Power (mW)
Quantity
Current (mA)
1
240
600 600 (mW)
Total Power
12644 (mW)
Table 9 Power for AAL1gator-8 w/COMET-QUADs
5V Components 74HCT138A (SOIC) LEDs 74HCT08 Misc, pullups/downs Total 5V Power
Quantity Current (mA) Power (mW)
1 3 1 1
100 15 3 100
500 225 15 500 1240 (mW)
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3.3V Components COMET-QUAD AAL1gator-8 FPGA GSI NBT SRAM Oscillators LEDs Buffers/Transceivers Misc. Total 3.3V Power 2.5V Components COMET-QUAD AAL1gator-8 Total 2.5V Power
Quantity
Current (mA)
Power (mW)
2 1 1 1 5 9 4 1
441 122 360 210 40 20 5.5 200
2910.6 402.6 1188 693 660 594 72.6 660 7181 (mW)
Power (mW)
Quantity
Current (mA)
2 1
38 240
190 600 790 (mW)
Total Power
9211 (mW)
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7
IMPLEMENTATION DESCRIPTION The AAL1gator-8 with COMETs and the AAL1gator-8 with COMET-QUADs reference design schematics were captured using Cadence software Concept Schematics Capture tool.
7.1
AAL1GATOR-8 with COMET Schematics Sheet 1: ROOT DRAWING This sheet provides an overview of the major functional blocks of the AAL1gator8 plus COMET reference design. Also, it illustrates the interconnections among the various blocks in the design. Groups of signals have been combined into a bus type name format even though these signals are not typically made into buses. This is done to make the schematic less cluttered and more readable and to utilize the capabilities of the schematic capture tool. Some examples of such signals are the TXTIP<7..0>, TL_DATA<7..0>, and TL_CLK<7..0>. Sheets 2-9: COMET BLOCK These sheets show the COMET devices and their power circuitry. The power circuitry includes a schottky diode for protection while powering up the COMET device and separate filtering circuitry for the analog and digital power pins. In addition, the JTAG port is connected among the 8 COMET devices, and the AAL1gator-8. Sheets 10-13: LINE INTERFACE These schematics show the termination, magnetic and protection circuitry for the line interface. A Pulse T9021, a quad 1:2.42 transformer included with two Surge Protector Diode Array, is used to couple four COMETs' transmit and receive lines to the connectors. The LC01-6 transient voltage suppressor (TVS) and the Raychem PTC provide over voltage protection. A single footprint is provided for both the bantam and RJ48C connectors. Sheet 14: FPGA BLOCK This sheet shows the interconnection of the Actel 42MX36 FPGA between the AAL1gator-8 and the COMET devices. The 1.544 MHz and 2.048 MHz oscillators are present to supply the XCLK signal to the COMET devices. The 38.88 MHz oscillator is present to supply the AAL1gator-8 system clock (SYSCLK) and the AAL1gator-8's ZBT RAM clock (RAM_CLK). The ATM
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Network clock is used by the FPGA to generate the 2.43 MHz NCLK. 0.1uF bulk capacitors are specified, and should be placed at the corners of the FPGA. The AAL1gator-8's clock synthesizer's interfaces are optionally provided to the FPGA in order to provide customization of SRTS or adaptive recovery algorithms. Note that the FPGA Mode pin is set to low except during the device programming and debugging. Note that the actual design of the FPGA has not been performed in this paper reference design. The FPGA design can be implemented with schematics or a hardware definition language. Sheet 15: MEMORY SYSTEM BLOCK This sheet indicates the connections between the system microprocessor, and the AAL1gator-8, COMET devices, and FPGA. 20 bit buffers and 16 bit data transceivers are present. Sheets 16-18: AAL1GATOR-8 BLOCK These sheets show how the AAL1gator-8 is connected into the system. Page 16 illustrates the AAL1gator-8's line interface, microprocessor interface, JTAG connections, power supply signal connections, and the decoupling capacitors. Note that the TLCLK_OE input pin is set high to make the TL_CLK pins as outputs between the time of hardware reset and when the CLK_SOURCE_TX bits are read. In the Direct mode, the Line_Mode pins are grounded. Page 17 shows the AAL1gator-8's RAM interface with a 256k x 18-bit pipelined GS841Z18 NBT SRAM. Since the RAM interface of the AAL1gator-8 is limited to 128k, the most significant bit of the SRAM is grounded. Bits 8 and 17 indicate odd parity for the lower and upper bytes, respectively. Page 18 shows the AAL1gator-8's UTOPIA connection to a UTOPIA L2 connector to provide access to the UTOPIA bus externally. Sheet 19: MICRO INTERFACE / POWER This page shows the connections between the system microprocessor and the reference design board. The LT1528 low drop out voltage regulator provides up to 3A at 3.3V to the board. The LT1118CST voltage regulator provides up to 0.500A at 2.5V to the AAL1gator-8 reference design. Both regulators should be in the DD package, so that no additional heat sink is required. Also, a pushbutton
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switch is included in the Reset circuitry to provide the hardware reset. This page is also included the JTAG port, the power and interrupt status LED circuitry. 7.2 AAL1GATOR-8 with COMET-QUAD Schematics Sheet 1: ROOT DRAWING This sheet provides an overview of the major functional blocks of the AAL1gator8 plus COMET-QUAD reference design. Also, it illustrates the interconnections among the various blocks in the design. Sheets 2-3: COMET-QUAD BLOCK These pages show the COMET-QUAD devices and their power circuitry. Separate filtering circuitry for the analog and digital power pins is included. In addition, the JTAG port is connected among the 2 COMET-QUAD devices, and the AAL1gator-8. The H-MVIP signal interface is also provided for the optional use. Sheets 4-7:LINE INTERFACE These schematic diagrams are the same as those for the COMET version. Sheet 8: FPGA BLOCK This sheet shows the interconnection of the FPGA between the AAL1gator-8 and the COMET-QUAD devices. The 1.544 MHz and 2.048 MHz oscillators are present to supply the XCLK signal to the COMET-QUAD devices. The38.88 MHz oscillator is present to supply the AAL1gator-8 system clock (SYSCLK) and the AAL1gator-8's ZBT RAM clock (RAM_CLK). The ATM network clock is used by the FPGA to generate the 2.43 MHz NCLK. The 4.096 MHz and 16.384 MHz oscillators are provided for H-MVIP mode's common clock and frame pulses. 0.1uF bulk capacitors are specified, and should be placed at the corners of the FPGA. Sheet 9: MEMORY SYSTEM BLOCK This sheet indicates the connections between the system microprocessor, and the AAL1gator-8, COMET-QUAD devices, and FPGA. 20 bit buffers and 16 bit data transceivers are present.
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Sheets 10-12: AAL1GATOR-8 BLOCK These schematic diagrams are the same as those for the COMET version, except the Line_Mode0 pin can be set to low for the Direct mode or high for the H-MVIP mode. Sheet 13: MICRO INTERFACE / POWER This page shows the connections between the system microprocessor and the reference design board. The LT1528 low drop out voltage regulator provides up to 3A at 3.3V to the board. The LT1118CST voltage regulator provides up to 0.750A at 2.5V to the AAL1gator-8 and COMET-QUAD devices. Both regulators should be in the DD package, so that no additional heat sink is required. Also, a pushbutton switch is included in the Reset circuitry to provide the hardware reset. This sheet is also included the JTAG port, the power and interrupt status LED circuitry.
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8
GLOSSARY AAL1 Any-PHY ATM CBR CES COS PHY SAR SCI-PHY SRTS UTOPIA VBR VC VCC VCI VP VPC VPI WAN ZBT ATM Adaptation Layer 1 Interoperable version of UTOPIA and SCI-PHY Asynchronous Transfer Mode Constant Bit Rate Circuit Emulation Services Class of Service Physical Layer Segmentation and Re-assembly PMC-Sierra enhanced UTOPIA bus Synchronous Residual Time Stamp Universal Test & Operations PHY Interface for ATM Variable Bit Rate Virtual Circuit Virtual Channel Connection Virtual Circuit Identifier Virtual Path Virtual Path Connection Virtual Path Identifier Wide Area Network Zero Bus Turnaround
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9
DEFINITIONS AAL (ATM Adaptation Layer) - The layer above the ATM layer that allows users to send packets larger than a cell. The ATM interface segments these packets, transmits the cells individually, and reassembles them at the other end. The AAL consists of two sub-layers: Convergence Sub-layer (CS) and Segmentation and Reassmbly (SAR). The AAL supports many kinds of services with different traffic characteristics and system requirements. AAL1 (ATM Adaptation Layer 1) - The layer above the ATM Layer in the ATM Protocol Model that handles adapting CBR traffic to an ATM network. Supports connection-oriented services that require constant bit rates and have specific timing and delay requirements. Examples are constant bit rate services like DS1 or DS3 transport. CBR (Constant Bit Rate) - Constant Bit Rate (CBR) is one of the five service categories of the ATM Layer. This service type allows a user to define a specific cell delay, cell delay variation (CDV), and reserves a specific and fixed bandwidth on the network. The CBR traffic includes voice, video, and circuit emulation (e.g., T1 Circuit emulation). Voice and video that has been compressed may have a variable transmission rate and therefore would not fit into this service class. CES (Circuit Emulation Service) - A service provided by ATM to emulate TDM circuits by not only passing bits through an ATM network but maintaining synchronization by providing end to end timing. SAR (Segmentation and Reassembly) - The Segmentation and Reassembly Layer is the lower of two sublayers (Convergence Sublayer (CS) and SAR) that make up the ATM Adaptation Layer (AAL) as shown in the diagram below. The SAR is responsible for mapping data from the AAL Convergence Sublayer into the cell payloads of an ATM cell stream. TDM (Time Division Multiplexing) - A method of multiplexing by which a transmission channel is divided into discrete time intervals
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10
REFERENCES 1. PMC-Sierra Inc., PMC-1970624, "Combined E1/T1 Transceiver Standard Product Data Sheet", November 2000, Issue 10. 2. PMC-Sierra Inc., PMC-1990315, "COMET-QUAD Data Sheet", May 2001, Issue 6. 3. PMC-Sierra Inc., PMC-2000097, "AAL1gator-8 Data Sheet", January 2000, Issue 1.
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11
DISCLAIMER This document is a paper reference design, and as such, has not been built or tested as of this date.
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12
APPENDIX A: BILL OF MATERIALS (COMET VERSION) Table 10 Ref. No U1 U2-9 U28-47 U15-16 U12 U55 U14 U51, U53 U52, U54 U11 U10 U56 U57 Y1 Major Components List 1 Component PM73123 AAL1gator-8 PM4351 COMET LC01-6 T9021 1:2.42 Transformer A42MX36 PQ208 FPGA GS841Z18 NBT SRAM MAX700 Power Supply Monitor 74FCT163827 FAST 20 Bit Buffer 74FCT163646 FAST 16 Bit Transceiver MC74HCT138AD 3-to-8 Decoder MCHCT541 8 Bit Buffer LT1528 Voltage Regulator LT1118CST Voltage Regulator HCMOS 38.880MHz, 50ppm Oscillator Manufacture PMC-Sierra Inc. PMC-Sierra Inc. SEMTECH Pulse Inc. ACTEL GSI Technology MAXIM IDT IDT Motorola Motorola Linear Technology Linear Technology MMD Components Package Type PBGA CABGA SMD SMD PQFP TQFP SOIC SOP SOP SOIC SOIC DD DD Half-size DIP Quantity 1 8 16 2 1 1 1 2 2 1 1 1 1 1
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Y2 Y3 F1 F2 SW1 TR1-32
HCMOS 1.544MHz, 50ppm Oscillator HCMOS 2.048MHz, 50ppm Oscillator 3.000A NANO 0.500A NANO Pushbutton switch TR250-180U Thermistor
MMD Components MMD Components Littlefuse Littlefuse
Half-size DIP Half-size DIP SMD Socket SMD Socket PBS
1 1 1 1 1 32 16
Raychem ADC Telecomm.
PTC
J1, J3, PC-834-C-Black Bantam J4, J6, Covers J7, J9, J10, J12, J13, J15, J16, J18, J19, J21, J22, J24
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13
APPENDIX B: BILL OF MATERIALS (COMET-QUAD VERSION) Table 11 Ref. No U1 U2-3 U20-23, U26-29, U32-35, U38-41 U5-6 U9 U7 U14 Major Components List 2 Component PM73123 AAL1gator-8 PM4354 COMET-QUAD LC01-6 Manufacture PMC-Sierra Inc. PMC-Sierra Inc. SEMTECH Package Type PBGA PBGA SMD Quantity 1 8 16
T9021 1:2.42 Transformer A42MX36 PQ208 FPGA GS841Z18 NBT SRAM MAX700 Power Supply Monitor
Pulse Inc. ACTEL GSI Technology MAXIM IDT IDT Motorola Motorola Linear Technology Linear Technology MMD
SMD PQFP TQFP SOIC SOP SOP SOIC SOIC DD DD Half-size
2 1 1 1 2 2 1 1 1 1 1
U44, U46 74FCT163827 FAST 20 Bit Buffer U45, U47 74FCT163646 FAST 16 Bit Transceiver U4 U11 U42 U43 Y1 MCHCT541 8 Bit Buffer MC74HCT138AD 3-to-8 Decoder LT1528 Voltage Regulator LT1118CST Voltage Regulator HCMOS 38.880MHz, 50ppm
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Oscillator Y2 Y3 Y4 Y5 F2 F1 SW1 TR1-32 J1, J3, J4, J6, J7, J9, J10, J12, J13, J15, J16, J18, J19, J21, J22, J24 HCMOS 1.544MHz, 50ppm Oscillator , HCMOS 2.048MHz, 50ppm Oscillator HCMOS 16.384MHz, 50ppm Oscillator HCMOS 4.096MHz, 50ppm Oscillator Littlefuse, 3.000A NANO Littlefuse, 0.750A NANO Pushbutton switch Raychem, TR250-180U Thermistor PC-834-C-Black Bantam Covers
Components MMD Components MMD Components MMD Components MMD Components Littlefuse Littlefuse . Raychem ADC Telecomm
DIP Half-size DIP Half-size DIP Half-size DIP Half-size DIP SMD Socket SMD Socket PBS PTC 1 1 1 1 1 1 1 32 16
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14
APPENDIX C: AAL1GATOR-8 W/COMETS SCHEMATICS
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APPENDIX D: AAL1GATOR-8 W/COMET-QUADS SCHEMATICS
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H PAGES 10-12 AAL1GATOR_8_BLOCK TL_DATA<7..0> TL_SIG<7..0> RL_DATA<7..0> RL_SIG<7..0> RL_SYNC<7..0> RL_CLK<7..0> AAL1_TDO PAGES 2-3 COMET_QUAD_BLOCK TXTIP<7..0> TXRING<7..0> TXCM<7..0> RXTIP<7..0> RXRING<7..0> PAGES 4-7 LINE_INTERFACE
H
TL_DATA<7..0> TL_SIG<7..0> RL_DATA<7..0> RL_SIG<7..0> RL_SYNC<7..0> G RL_CLK<7..0> AAL1_TDO
TL_DATA<7..0> TL_SIG<7..0> RL_DATA<7..0> RL_SIG<7..0> RL_SYNC<7..0> RL_CLK<7..0>
TXTIP<7..0> TXRING<7..0> TXCM<7..0> RXTIP<7..0> RXRING<7..0> TRSTB
TXTIP<7..0> TXRING<7..0> TXCM<7..0> RXTIP<7..0> RXRING<7..0> G
AAL1_TDO
TCK TDO1 TMS IRQ2_BUS<1..0>
PAGE 8 FPGA_BLOCK TL_CLK<7..0> TL_SYNC<7..0> CGC_SER_D CGC_VALID F CGC_DOUT<3..0> CGC_LINE<3..0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK TL_CLK<7..0> TL_SYNC<7..0> CGC_SER_D CGC_VALID CGC_DOUT<3..0> CGC_LINE<3..0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK TL_CLK<7..0> TL_SYNC<7..0> CGC_SER_D CGC_VALID CGC_DOUT<3..0> CGC_LINE<3..0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK CS3B WRB RDB E PAGE 13 MICRO INTERFACE AAL1_CSB AAL1_ACKB AAL1_INTB AAL1_CSB AAL1_ACKB AAL1_INTB AAL1_CSB PAGE 9 AAL1_ACKB AAL1_INTB RDB_IN WRB_IN RSTB D RSTB RDB WRB COMETQ_CSB<1..0> MEMORY_SYSTEM_BLOCK USED IN H-MVIP MODE C4B C4B C4B C16B C16B C16B RSTB COMETQ_FPGA_A<2..0> COMETQ_FPGA_D<7..0> COMETQ_FPGA_A<2..0> CMV8MCLK CMVFPC CMVFPB USED IN H-MVIP MODE CMV8MCLK CMVFPC CMVFPB BTCLK<7..0> BTFP<7..0> XCLK<1..0> BTCLK<7..0> BTFP<7..0> XCLK<1..0> BTCLK<7..0> BTFP<7..0> XCLK<1..0>
RSTB WRB RDB COMETQ_FPGA_D<7..0> COMETQ_FPGA_A<10..0> COMETQ_CSB<1..0> F
CMV8MCLK CMVFPC CMVFPB
<2..0>
E
COMETQ_CSB<1..0>
RDB WRB D
COMETQ_FPGA_A<10..0> TMS TCK TRSTB TDI C UP_A<21..0> UP_D<15..0> CS2B RDB_IN WRB_IN CS3B RSTB IRQ2_BUS<1..0> COMETQ_FPGA_D<7..0> TMS TCK TRSTB TDI AAL1_A<19..0> AAL1_D<15..0> AAL1_A<19..0> AAL1_D<15..0> AAL1_A<19..0> AAL1_D<15..0>
COMETQ_FPGA_A<10..0> COMETQ_FPGA_D<7..0>
C
UP_A<21..0> UP_D<15..0> CS2B RDB_IN WRB_IN CS3B RSTB B IRQ2_BUS<1..0> DEV_SELB TMS TDO1 TCK TRSTB TDI
UP_A<21..0> RDB_IN UP_D<15..0> CS2B WRB_IN
DEV_SELB
B
PMC-Sierra, Inc.
A DRAWING TITLE=AAL_ROOT ABBREV=AAL_ROOT LAST_MODIFIED=Fri Jan 21 10:30:26 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN ROOT DRAWING ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:1 TRUE 1 OF 13 A
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H
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PBGA U2 PBGA U2 G
5D10< 5G10< 4D10< 4G10<
8F2>
BTCLK<7..0>\I
COMET-QUAD PM4354 1 OF 4
3 M14 2 L2 1 H16 0 F3 3 M15 2 M3 1 J14 0 G3 3 N13 2 M1 1 H14 0 H4 3 M16 2 M4 1 H13 0 F4 330 R72 K2 K1 L4 K3 F1 F2
TXTIP<3>\I TXTIP<2>\I TXTIP<1>\I TXTIP<0>\I
R13 P4 A13 B4 T11 R6 A11 B6
COMET-QUAD PM4354 TXTIP1<4> 2 OF 4 TXTIP1<3> TXTIP1<2> TXTIP1<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1>
RXTIP<4> RXTIP<3> RXTIP<2> RXTIP<1>
N10 P7 D10 C7 P10 T7 C10 A7 P9 T8 C9 A8 T15 J13 L16 R16 R15 T16 P8 D8 J4 TP4 J15 TP5 N3 TP6 L14 TP7
RXTIP<3>\I RXTIP<2>\I RXTIP<1>\I RXTIP<0>\I RXRING<3>\I RXRING<2>\I RXRING<1>\I RXRING<0>\I
5B10> 5F10> 4B10> 4F10> 5B10> 5E10> 4B10> 4E10>
BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1>
BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1> BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1>
N16 3 N1 2 F16 1 E2 0 P16 P2 G15 E3 3 2 1 0
RL_CLK<7..0>\I
3G2> 10C10<
G RL_SIG<7..0>\I
3G2> 10C10<
10C5>
TL_SIG<7..0>\I
RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC PIO RES<7> RES<6> RES<5> RES<4> 1 RES<3> 1 RES<2> 1 RES<1> 1
8E2>
BTFP<7..0>\I
5C10< 5G10< 4C10< 4G10<
TXRING<3>\I TXRING<2>\I TXRING<1>\I TXRING<0>\I
T13 R4 C13 A3 R11 N5 B11 D5
P15 3 R1 2 G14 1 E4 0 N15 P1 F13 E1 3 2 1 0
RL_SYNC<7..0>\I
3G2> 10D10<
10D5>
TL_DATA<7..0>\I
RL_DATA<7..0>\I
3F2> 10D10<
XCLK<0>\I
330 R9
8C2>
F
5D10> 5G10> 4D10> 4G10>
0
TXCM<3>\I TXCM<2>\I TXCM<1>\I TXCM<0>\I
N12 P5 D12 C5
8E2> 8D2> 8D2>
R11
CMV8MCLK\I CMVFPC\I CMVFPB\I
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM
F
0.01UF
0.01UF
0.01UF
R12
R94
100K
C11 100K
C19 100K
C13 100K
R98
LINE
0.01UF
E E 3.3 V
4.7 22UF + R1 0.01UF 4.7 C1 22UF + R102 0.01UF C33 C35 C2
C27
R8
3.3 V PBGA U2
R14 C8 T9 R8 B9 B8 0.47UF
3.3 V
1 0.47UF R4 0.01UF
3.3 V
1 0.47UF C9 R18 0.01UF
3.3 V
1 0.47UF C17 R96 0.01UF
3.3 V
QAVD<2> QAVD<1> RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1>
COMET-QUAD PM4354 QAVS<2> 4 OF 4 QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER
T14 D9 R9 N7 A9 D7 R10 N6 B10 D6
C6
C14
1 C25 R2 0.01UF C4 C3
C21
T10 R7 A10 B7 P11 T6 C11 A6
D
3.3 V
1 0.1UF R10 0.01UF
3.3 V
1 C10 0.1UF R89 0.01UF
3.3 V
1 C18 0.1UF R97 0.01UF
3.3 V
D
N11 P6 D11 C6 R12 N4 B12 C4 T12 R5 A12 B5 L15 K16 G13 L3 J3 H1 G2 C14 M2 P14 L13 F14 R2 J2 D1 B2 K13 G4 J7 J8 J9 J10 K7 K8 K9 K10
C7
C15
1 C26 0.1UF R100 0.01UF P13 T4 D13 A4 P12 T5 C12 A5 J16 M13 K15 H15 L1 J1 H3 G1 N14 G16 N2 K4 D4 C3 K14 H2 C29 C31
3.3 V
1 R3 47UF C5 0.01UF
3.3 V
1 C8 R13 C12 47UF 0.01UF
3.3 V
1 C16 R95 C20 47UF 0.01UF
C22
3.3 V
1 C24 R99 C28 47UF 0.01UF C30
C
2.5 V
VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
C
9D1>
COMETQ_FPGA_A<10..0>\I
0.01UF
B
3A10< 11E2> 13G5> 13H5> 13G5>
TDO0 AAL1_TDO\I TCK\I TMS\I TRSTB\I
T1 T3 T2 R3 P3
D14 E15 E16 E14 F15 E13
RDB\I WRB\I COMETQ_CSB<0>\I IRQ2_BUS<0>\I RSTB\I
9C1> 9C1> 9B1> 13E2< 13F5>
22UF
10 9 8 7 6 5 4 3 2 1 0
D15 D16 C16 C15 B16 A16 B15 A15 B14 A14 B13
PBGA U2 COMET-QUAD PM4354 3 OF 4 D<7> A<10> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> RDB WRB TDO CSB TDI ALE TCK INTB TMS RSTB TRSTB MICRO_JTAG
3.3 V
D3 D2 C2 C1 B1 A1 A2 B3 7 6 5 4 3 2 1 0
COMETQ_FPGA_D<7..0>\I 3.3 V
4.7K
3B7<> 9E1<> 8C9<
3.3 V
R7 4.7 R101 C32
N8 N9 G7 G8 G9 G10 H7 H8 H9 H10 C34
B
DRAWING: COMET_Q_1 COMETQ Thu May 17 11:12:19 2001
3.3 V
2.5 V
PMC-Sierra, Inc.
0.01UF C40 0.01UF C39 0.01UF C38 0.01UF 0.01UF 0.01UF C37 0.01UF C41 0.01UF C146 C147 C23
A
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 2 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN COMET_QUAD_1 ENGINEER: WT 2
ISSUE DATE: 01/05/16 REVISION NUMBER: 1.1 PAGE:2 1 OF 13
A
DECOUPLING CAPS: ONE PER TWO POWER PINS
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
U3 COMET-QUAD PM4354 1 OF 4
7 M14 6 L2 5 H16 4 F3 7 M15 6 M3 5 J14 4 G3 7 N13 6 M1 5 H14 4 H4 7 M16 6 M4 5 H13 4 F4 330 R73 K2 K1 L4 K3 F1 F2
U3 G
7D10< 7G10< 6D10< 6G10<
8F2>
BTCLK<7..0>\I
TXTIP<7>\I TXTIP<6>\I TXTIP<5>\I TXTIP<4>\I
R13 P4 A13 B4 T11 R6 A11 B6
COMET-QUAD PM4354 TXTIP1<4> 2 OF 4 TXTIP1<3> TXTIP1<2> TXTIP1<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1>
RXTIP<4> RXTIP<3> RXTIP<2> RXTIP<1>
N10 P7 D10 C7 P10 T7 C10 A7 P9 T8 C9 A8 T15 J13 L16 R16 R15 T16 P8 D8 J4 TP8 J15 TP9 N3 TP10 L14 TP11
RXTIP<7>\I RXTIP<6>\I RXTIP<5>\I RXTIP<4>\I RXRING<7>\I RXRING<6>\I RXRING<5>\I RXRING<4>\I
7B10> 7F10> 6B10> 6F10> 7B10> 7E10> 6B10> 6E10>
BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1>
BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1> BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1>
N16 N1 F16 E2 P16 P2 G15 E3 P15 R1 G14 E4 N15 P1 F13 E1
7 6 5 4 7 6 5 4 7 6 5 4 7 6 5 4
RL_CLK<7..0>\I
2G2>10C10<
G RL_SIG<7..0>\I
2G2>10C10<
10C5>
TL_SIG<7..0>\I
RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC PIO RES<7> RES<6> RES<5> RES<4> 1 RES<3> 1 RES<2> 1 RES<1> 1
8E2>
BTFP<7..0>\I
RL_SYNC<7..0>\I
2G2>10D10<
7C10< 7G10< 6C10< 6G10<
TXRING<7>\I TXRING<6>\I TXRING<5>\I TXRING<4>\I
T13 R4 C13 A3 R11 N5 B11 D5
10D5>
TL_DATA<7..0>\I
RL_DATA<7..0>\I
2F2>10D10<
XCLK<1>\I
330 R17
8C2>
F
0 R106
7D10> 7G10> 6D10> 6G10>
TXCM<7>\I TXCM<6>\I TXCM<5>\I TXCM<4>\I
N12 P5 D12 C5
8E2> 8D2> 8D2>
CMV8MCLK\I CMVFPC\I CMVFPB\I
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM
F
0.01UF
0.01UF
0.01UF
R107
R111
R115
100K
C47 100K
C54 100K
C58 100K
R116
LINE
0.01UF
E E 3.3 V
4.7 22UF + R117 0.01UF 4.7 C67 22UF + R122 0.01UF C72 C74 C63
C62
3.3 V U3
R14 C8 T9 R8 B9 B8 0.47UF
3.3 V
1 0.47UF R104 0.01UF
3.3 V
1 0.47UF C45 R109 0.01UF
3.3 V
1 0.47UF C52 R113 0.01UF
3.3 V
QAVD<2> QAVD<1> RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1>
COMET-QUAD PM4354 QAVS<2> 4 OF 4 QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER
T14 D9 R9 N7 A9 D7 R10 N6 B10 D6
C42
C49
1 C60 R119 0.01UF C65 C69
C56
T10 R7 A10 B7 P11 T6 C11 A6
D
3.3 V
1 0.1UF R105 0.01UF
3.3 V
1 C46 0.1UF R110 0.01UF
3.3 V
1 C53 0.1UF R114 0.01UF
3.3 V
D
N11 P6 D11 C6 R12 N4 B12 C4 T12 R5 A12 B5 L15 K16 G13 L3 J3 H1 G2 C14 M2 P14 L13 F14 R2 J2 D1 B2 K13 G4 J7 J8 J9 J10 K7 K8 K9 K10
C43
C50
1 C61 0.1UF R120 0.01UF P13 T4 D13 A4 P12 T5 C12 A5 J16 M13 K15 H15 L1 J1 H3 G1 N14 G16 N2 K4 D4 C3 K14 H2 C66 C70
3.3 V
1 R103 C36 47UF 0.01UF
3.3 V
1 C44 R108 C48 47UF 0.01UF
3.3 V
1 C51 R112 C55 47UF 0.01UF
C57
3.3 V
1 C59 R118 C64 47UF 0.01UF C68
C
2.5 V
VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
C
3.3 V
U3 COMETQ_FPGA_A<10..0>\I COMET-QUAD PM4354 3 OF 4 D<7> A<10> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> RDB WRB TDO CSB TDI ALE TCK INTB TMS RSTB TRSTB MICRO_JTAG
3.3 V
D3 D2 C2 C1 B1 A1 A2 B3 D14 E15 E16 E14 F15 E13 7 6 5 4 3 2 1 0
C71
22UF
C73
9D1>
B
10 9 8 7 6 5 4 3 2 1 0
D15 D16 C16 C15 B16 A16 B15 A15 B14 A14 B13 T1 T3 T2 R3 P3
COMETQ_FPGA_D<7..0>\I 3.3 V
4.7K R16
0.01UF
4.7 R121
N8 N9 G7 G8 G9 G10 H7 H8 H9 H10
2C7<> 9E1<> 8C9<
B
DRAWING: COMET_Q_2 COMETQ Thu May 17 11:12:24 2001
13G5< 2B10> 13G5> 13H5> 13G5>
TDO1\I TDO0 TCK\I TMS\I TRSTB\I
RDB\I 9C1> WRB\I 9C1> COMETQ_CSB<1>\I 9B1> IRQ2_BUS<1>\I RSTB\I
13E2< 13F5>
3.3 V
2.5 V
PMC-Sierra, Inc.
0.01UF C75 0.01UF C76 0.01UF C77 0.01UF 0.01UF 0.01UF C78 0.01UF C81 0.01UF C79 C80 C82
A
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 2 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN COMET_QUAD_2 ENGINEER: WT 2
ISSUE DATE: 01/05/16 REVISION NUMBER: 1.1 PAGE:3 1 OF 13
A
DECOUPLING CAPS: ONE PER TWO POWER PINS
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 T TN RN R S
J1
T TN RN R S
2G10>
TXTIP<0>\I
12.7 R22
16 15 14 13 12 11 10 9
TR1
R39
2F10<
TXCM<0>\I
12.7 R23
4.7UF + C83 1
U5
T9021
1:2.42
40
U20
LC01-6
BANTAM
1 2 3 4 5 6 7 8
G
TR250-180
G
2F10>
TXRING<0>\I
3
38
TR2
3.3 V
2 TR250-180 100 16 15 14 13 12 11 10 9 7 TR3 R38 T TN RN R S
J3
T TN RN R S
F
F BANTAM
U21
2G6<
RXTIP<0>\I
4
1:2.42
37
18.2
5 R24
36
1 2 3 4 5 6 7 8
LC01-6
TR250-180
2G6<
RXRING<0>\I
TR4
E E
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 R19 T TN RN R S
J4
T TN RN R S
D
2G10>
TXTIP<1>\I
12.7 R25
6
1:2.42
16 15 14 13 12 11 10 9
TR5
35
D BANTAM
8 4.7UF + C84
33
1 2 3 4 5 6 7 8
2F10<
TXCM<1>\I
12.7 R26
U22
LC01-6
TR250-180
TR6
2F10>
TXRING<1>\I
C
9
C
1:2.42
32 TR250-180 100 10 31 16 15 14 13 12 11 10 9 TR7 R20 T TN RN R S
J6
T TN RN R S
BANTAM LC01-6
2G6<
18.2
R27
U23
1 2 3 4 5 6 7 8
RXTIP<1>\I
B RXRING<1>\I
B
TR250-180
2G6<
TR8
100K R21
TP1 T
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu May 17 11:11:58 2001 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN LINE INTERFACE 1 ENGINEER: 3 KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:4 TRUE 1 OF 13 A
A
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 T TN RN R S
J7
T TN RN R S
2G10>
TXTIP<2>\I
12.7 R32
16 15 14 13 12 11 10 9
TR9
R28
2F10<
TXCM<2>\I
12.7 R33
4.7UF + C85 11
U5
T9021
1:2.42
30
U26
LC01-6
BANTAM
1 2 3 4 5 6 7 8
G
TR250-180
G
13
28
TR10
2F10>
TXRING<2>\I 3.3 V
12
TR250-180 100 17 16 15 14 13 12 11 10 9 TR11 R29 T TN RN R S
J9
T TN RN R S
F RXTIP<2>\I
14
F BANTAM
2G6<
1:2.42
27
18.2
15 R34
26 1 2 3 4 5 6 7 8
U27
LC01-6
TR250-180
2G6<
RXRING<2>\I
TR12
E E
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 R30 T TN RN R S
J10
T TN RN R S
2G10>
16
25
D
12.7 R35 18 23
16 15 14 13 12 11 10 9
TXTIP<3>\I
1:2.42
TR13
D BANTAM
1 2 3 4 5 6 7 8
2F10<
TXCM<3>\I
12.7 R36
4.7UF + C86
U28
LC01-6
TR250-180
TR14
2G10>
TXRING<3>\I
C
19
C
1:2.42
22 TR250-180 100 20 21 TR15 16 15 14 13 12 11 10 9 R31 T TN RN R S
J12
T TN RN R S
BANTAM LC01-6
2G6<
18.2
R37
U29
1 2 3 4 5 6 7 8
RXTIP<3>\I
B RXRING<3>\I
B
TR250-180
2G6<
TR16
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu May 17 11:12:00 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN LINE INTERFACE 2 ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:5 TRUE 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 T TN RN R S
J13
T TN RN R S
3G10>
TXTIP<4>\I
12.7 R49
16 15 14 13 12 11 10 9
TR17
R40
3F10<
TXCM<4>\I
12.7 R48
4.7UF + C87 1
U6
T9021
1:2.42
40
U32
LC01-6
BANTAM
1 2 3 4 5 6 7 8
G
TR250-180
G
3F10>
TXRING<4>\I
3
38
TR18
3.3 V
2 TR250-180 100 16 15 14 13 12 11 10 9 7 TR19 R41 T TN RN R S
J15
T TN RN R S
F
F BANTAM
18.2
R47
U33
3G6<
RXTIP<4>\I
4
1:2.42
37
5
36
1 2 3 4 5 6 7 8
LC01-6
TR250-180
3G6<
RXRING<4>\I
TR20
E E
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 R42 T TN RN R S
J16
T TN RN R S
D
3G10>
TXTIP<5>\I
12.7 R46
6
1:2.42
16 15 14 13 12 11 10 9
TR21
35
D BANTAM
8 4.7UF + C88
33
1 2 3 4 5 6 7 8
3F10<
TXCM<5>\I
12.7 R45
U34
LC01-6
TR250-180
TR22
3F10>
TXRING<5>\I
C
9
C
1:2.42
32 TR250-180 100 10 31 16 15 14 13 12 11 10 9 TR23 R43 T TN RN R S
J18
T TN RN R S
BANTAM LC01-6
3G6<
18.2
R44
U35
1 2 3 4 5 6 7 8
RXTIP<5>\I
B RXRING<5>\I
B
TR250-180
3G6<
TR24
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu May 17 11:12:06 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN LINE INTERFACE 3 ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:6 TRUE 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 T TN RN R S
J19
T TN RN R S
3G10>
TXTIP<6>\I
12.7 R55
16 15 14 13 12 11 10 9
TR25
R56
3F10<
TXCM<6>\I
12.7 R54
4.7UF + C89 11
U6
T9021
1:2.42
30
U38
LC01-6
BANTAM
1 2 3 4 5 6 7 8
G
TR250-180
G
13
28
TR26
3F10>
TXRING<6>\I 3.3 V
12
TR250-180 100 17 16 15 14 13 12 11 10 9 TR27 R57 T TN RN R S
J21
T TN RN R S
F RXTIP<6>\I
14
F BANTAM
3G6<
1:2.42
27
18.2
15 R53
26 1 2 3 4 5 6 7 8
U39
LC01-6
TR250-180
3G6<
RXRING<6>\I
TR28
E E
TR250-180
TIP AND RING SC FOR OPTIONAL CHOKE PLACEMENT
100 R58 T TN RN R S
J22
T TN RN R S
3G10>
16
25
D
12.7 R52 18 23
16 15 14 13 12 11 10 9
TXTIP<7>\I
1:2.42
TR29
D BANTAM
1 2 3 4 5 6 7 8
3F10<
TXCM<7>\I
12.7 R51
4.7UF + C90
U40
LC01-6
TR250-180
TR30
3G10>
TXRING<7>\I
C
19
C
1:2.42
22 TR250-180 100 20 21 TR31 16 15 14 13 12 11 10 9 R59 T TN RN R S
J24
T TN RN R S
BANTAM LC01-6
3G6<
18.2
R50
U41
1 2 3 4 5 6 7 8
RXTIP<7>\I
B RXRING<7>\I
B
TR250-180
3G6<
TR32
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu May 17 11:12:09 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN LINE INTERFACE 4 ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:7 TRUE 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H PLACE ONE CAP ON EACH SIDE OF THE FPGA. 3.3 V
H
3.3 V
0.1UF 0.1UF C103 0.1UF C104 C102 0.1UF C101
183 136 133 130 79 32 29 17 2 202 182 164 132 98 80 60 28
106
U9
VCCA<9> VCCA<8> VCCA<7> VCCA<6> VCCA<5> VCCA<4> VCCA<3> VCCA<2> VCCA<1> VCCI<8> VCCI<7> VCCI<6> VCCI<5> VCCI<4> VCCI<3> VCCI<2> VCCI<1>
VCC
G
G
13F5> 13E5> 9C1> 9C1>
RSTB\I CS3B\I RDB\I WRB\I
10D5<>
TL_SYNC<7..0>\I IN H-MVIP MODE TL_SYNC<0> IS F0B
F
10C5<>
TL_CLK<7..0>\I
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3
10E10< 10E10< 10F10>
CGC_VALID\I CGC_SER_D\I CGC_DOUT<3..0>\I
USED FOR EXTERNAL ADAPTIVE ALGORITHM CGC_LINE<3..0>\I 10E10> E
10E10> 10E10>
ADAP_STRB\I SRTS_STRB\I
77 76 75 74 73 72 71 70 69 68 67 66 64 63 62 61 59 58 57 56 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 127 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 104 102 101 100 99 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 65 91
IO_A<41> IO_A<40> IO_A<39> IO_A<38> IO_A<37> IO_A<36> IO_A<35> IO_A<34> IO_A<33> IO_A<32> IO_A<31> IO_A<30> IO_A<29> IO_A<28> IO_A<27> IO_A<26> IO_A<25> IO_A<24> IO_A<23> IO_A<22> IO_A<21> IO_A<20> IO_A<19> IO_A<18> IO_A<17> IO_A<16> IO_A<15> IO_A<14> IO_A<13> IO_A<12> IO_A<11> IO_A<10> IO_A<9> IO_A<8> IO_A<7> IO_A<6> IO_A<5> IO_A<4> IO_A<3> IO_A<2> IO_A<1> IO_B<41> IO_B<40> IO_B<39> IO_B<38> IO_B<37> IO_B<36> IO_B<35> IO_B<34> IO_B<33> IO_B<32> IO_B<31> IO_B<30> IO_B<29> IO_B<28> IO_B<27> IO_B<26> IO_B<25> IO_B<24> IO_B<23> IO_B<22> IO_B<21> IO_B<20> IO_B<19> IO_B<18> IO_B<17> IO_B<16> IO_B<15> IO_B<14> IO_B<13> IO_B<12> IO_B<11> IO_B<10> IO_B<9> IO_B<8> IO_B<7> IO_B<6> IO_B<5> IO_B<4> IO_B<3> IO_B<2> IO_B<1> QCLKA_IO QCLKB_IO MODE DCLK_IO SDI_IO PRA_IO PRB_IO TMS_IO TDI_IO TDO_IO TCK_IO
IO_C<40> IO_C<39> IO_C<38> IO_C<37> IO_C<36> IO_C<35> IO_C<34> IO_C<33> IO_C<32> IO_C<31> IO_C<30> IO_C<29> IO_C<28> IO_C<27> IO_C<26> IO_C<25> IO_C<24> IO_C<23> IO_C<22> IO_C<21> IO_C<20> IO_C<19> IO_C<18> IO_C<17> IO_C<16> IO_C<15> IO_C<14> IO_C<13> IO_C<12> IO_C<11> IO_C<10> IO_C<9> IO_C<8> IO_C<7> IO_C<6> IO_C<5> IO_C<4> IO_C<3> IO_C<2> IO_C<1>
26 25 24 23 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 4 208 206 205 204 203 201 200 199 198 197 195 194 193 192 191 190 189 187 185
F RN2 68
1 2 3 4 5 6 7 8
RES_ARRAY_8
16 15 14 13 12 11 10 9
7 6 5 4 3 2 1 0
BTCLK<7..0>\I
2G6< 3G6<
7 6 5 4 3 2 1 0
BTFP<7..0>\I
2G6< 3G6<
E
3.3 V
50PPM 3.3V 16.384MHZ HCMOS Y4
8 C99 4
0.01UF
0.1UF
C100
VDD
OUT
5 1
22 R14
GND NC/TS
D 3.3 V
50PPM 3.3V 4.096MHZ HCMOS Y5
8
H-MVIP COMMON CLOCK AND FRAME PLUSE CLOCK
VDD
OUT
5 1
22 R15
C98 0.01UF
4 C97
0.1UF
GND NC/TS
11E7< 9E1<> 3B7<> 2C7<>
RAM_CLK\I COMETQ_FPGA_D<7..0>\I
C
3.3 V
50PPM 3.3V 38.880MHZ HCMOS Y1
8
9D1> 10E5<
COMETQ_FPGA_A<2..0>\I AAL1_SYSCLK\I NCLK\I
R6 22
7 6 5 4 3 2 1 0 2 1 0
VDD
OUT
5 1
0.01UF
0.1UF
4 C95
C96
GND NC/TS
NETWORK_CLK
10K R60
2 1
3.3 V HEADER2 J2
IO_D<40> IO_D<39> IO_D<38> IO_D<37> IO_D<36> IO_D<35> IO_D<34> IO_D<33> IO_D<32> IO_D<31> IO_D<30> IO_D<29> IO_D<28> IO_D<27> IO_D<26> IO_D<25> IO_D<24> IO_D<23> IO_D<22> IO_D<21> IO_D<20> IO_D<19> IO_D<18> IO_D<17> IO_D<16> IO_D<15> IO_D<14> IO_D<13> IO_D<12> IO_D<11> IO_D<10> IO_D<9> IO_D<8> IO_D<7> IO_D<6> IO_D<5> IO_D<4> IO_D<3> IO_D<2> IO_D<1> QCLKC_IO QCLKD_IO CLKA_IO CLKB_IO GND_<1> GND_<2> GND_<3> GND_<4> GND_<5> GND_<6> GND_<7> GND_<8> GND_<9> GND_<10> GND_<11> GND_<12> GND_<13>
181 179 177 176 175 174 173 172 170 169 168 167 166 165 163 162 161 160 158 156 155 154 153 152 151 149 148 147 146 145 144 143 142 141 140 139 138 137 135 134 196 171 180 186
USED IN H-MVIP MODE C4B\I C16B\I CMV8MCLK\I CMVFPC\I CMVFPB\I
10B10< 10B5< 2F6< 3F6< 2F6< 3F6< 2F6< 3F6<
D
C RN1
1 2 3 4
68
8 7 6 5 1 0
XCLK<1..0>\I 3.3 V
2F7< 3F6<
C94
J26 B
5
MODE = GND, EXCEPT DURING DEVICE PROGRAMMING AND DEBUGGING
3
207 159 178 188 54 55 103 128
1
A42MX36_PQ208
NC/TS GND
4
2
50PPM 2.048MHZ HCMOS 3.3V Y3
22 R86 5 1 0.01UF
C93
OUT
VDD
0.1UF
R74
5
8
0.01UF
3
22
50PPM 1.544MHZ HCMOS 3.3V Y2
3.3 V
B
OUT
VDD
8 C91 4 C92 0.1UF
SMA
4 1 1 22 27 52 53 78 105 126 129 131 150 157 184
NC/TS GND
J25
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMC-Sierra, Inc.
P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10 P_11 P_12 P_13 P_14
HDR14
A
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=FPGA_BLOCK ABBREV=FPGA_BLOCK LAST_MODIFIED=Thu May 17 11:12:30 2001 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN FPGA BLOCK ENGINEER: 3 KM 2
ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:8 1 OF 13
A
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
AAL1_A<19..0>\I
ZONE
10G10<
REV
DESCRIPTION
DATE
APPR
H U44 74FCT163827 A 10 10 Y A9 A8 A7 A6 A5 A4 A3 A2 A1 OE2
330 R61 0.01UF 56 1
3.3 V
H
C107 0.01UF
0.01UF
C108 0.01UF
C106 0.01UF C110 0.1UF
19 43 18 44 17 45 16 47 15 48 14 49 13 51
14 19 13 18 12 17 10 16 9 8 6 5 3 2 15 14 13
Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE1
PLACE CAPS NEAR EACH IC 3.3 V
C112 0.1UF
0.1UF
C111 0.1UF
C105
12 52 11 54 10 55
12 11 10
VCC
C114
0.1UF
3.3 V F
30 31 33 34 36 37 38 40 41 42
C113
C109
G
G
RN3 4.7K
9 8 7 6 5 4 3 2
27 26 24 23 21 20 19 17 16 15
9 8 7 6 5
A9 A8 A7 A6 A5 A4 A3 A2 A1 OE2
29 330 R62 28
Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE1
U47
4 3 2 1 0 7 6 5 4 3 2 1 0 24 23 21 20 19 17 16 15 27 30 26 31
A 163646 B8 8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 CLKAB CLKBA SAB SBA DIR OE
74FCT
E
1 0
33 34 36 37 38 40 41 42
1 2 3 4 5 6 7 8
RES_ARRAY_8
U44 74FCT163827 10 A 10 Y
F
16 15 14 13 12 11 10 9
7 6 5 4 3 2 1 0
E COMETQ_FPGA_D<7..0>\I
2C7<> 3B7<> 8C9<
330
R71
28
13E5>
UP_A<21..0>\I
13E5>
DEV_SELB\I
D
29
13D10<>
UP_D<15..0>\I AAL1_D<15..0>\I
10F5<>
D
COMETQ_FPGA_A<10..0>\I U45
15 14 13 12 11 10 9 8 24 23 21 20 19 17 16 15 27 30 26 31 330 R63
2C10< 3B10< 8C9<
74FCT A 163646
8 A7 A6 A5 A4 A3 A2 A1
B8 B7 B6 B5 B4 B3 B2 B1
33 34 36 37 38 40 41 42
15 14 13 12 11 10 9 8
0 1 2 3 4 5 6 7
43 44 45 47 48 49 51 52 54 55
U46 74FCT163827 10 A 10 Y A9 A8 A7 A6 A5 A4 A3 A2 A1 OE2
56 1
14 13 12 10 9 8 6 5 3 2
0
Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE1
RDB\I
1 2 3 4 5 6 7 8 9
2B7< 3B7< 8G9<
WRB\I
C
4.7K
3.3 V
R64
CLKAB CLKBA SAB SBA DIR OE
2B7< 3B7< 8G9<
C
28
29 R65
330
8 9
3.3 V 4.7K U45
7 6 5 4 3 2 1 0 14 13 12 10 9 8 6 5 2 55 3 54 330 R67 330 R70
B8 B7 B6 B5 B4 B3 B2 B1
U11
8 7 6 5
74FCT A 163646
8 A7 A6 A5 A4 A3 A2 A1
B
43 44 45 47 48 49 51 52
7 6 5 4 3 2 1 0
MC74HCT138AD
HCT138
DEMUX
13E5> 13E5>
RDB_IN\I WRB_IN\I
10
30 31 33 34 20 21 36 37 38 40 41 42
U46 74FCT163827 10 A 10 Y A9 A8 A7 A6 A5 A4 A3 A2 A1 OE2
29
RN5
27 26 24 23 21 20 19 17 16 15 10
Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE1
28
3 2 1
S2 S1 S0
3.3 V
1
56
4.7K
R68
13E5>
R66
CS2B\I
6 4 5
CLKAB CLKBA SAB SBA DIR OE
RN4 1 330 2
3 4
8 7 6 5
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
7 9 10 11 12 13 14 15
B
1 2 3 4
1 0
COMETQ_CSB<1..0>\I
2B7< 3B7<
EN EN EN 1 2A 2B
PMC-Sierra, Inc.
DRAWING TITLE=MEMORY_SYSTEM_BLOCK ABBREV=MEMORY_SYSTEM_BLOCK LAST_MODIFIED=Thu May 17 11:12:43 2001 DOCUMENT NUMBER: 991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN MEMORY SYSTEM BLOCK ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:9 1 OF 13 A
A
330
330 R69
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
9H6>
AAL1_A<19..0>\I
F
8E9<
CGC_DOUT<3..0>\I
8E9<
CGC_LINE<3..0>\I SRTS_STRB\I ADAP_STRB\I NCLK\I CGC_SER_D\I CGC_VALID\I
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0
E
8E9< 8E9< 8C9> 8E9> 8F9>
W2 Y2 AA1 AB1 AB4 AA5 Y6 Y3 AB6 W6 Y8 AA8 W9 Y10 AA10 AB10 W12 AA12 Y12 W13 AB16 AB14 Y15 AA15 AB19 AA18 W19 AB18 AA20 AA19 AA16 Y16 AA17 W18
U1 AAL1GATOR-8 PM73123 2 OF 5 A19 A18 A17 A16 D15 A15 D14 A14 D13 A13 D12 A12 D11 A11 D10 A10 D9 D8 A9 D7 A8 D6 A7 D5 A6 D4 A5 D3 A4 D2 A3 D1 A2 D0 A1 A0 ALE CGC_DOUT3 WRB CGC_DOUT2 RDB CGC_DOUT1 CSB CGC_DOUT0 ACKB CGC_LINE3 INTB CGC_LINE2 TRSTB CGC_LINE1 RSTB CGC_LINE0 SYSCLK SRTS_STB SCAN_MODEB ADAP_STB TCLK NCLK TMS TL_CLK_OE TDI CGC_SER_D TDO CGC_VALID MICRO/JTAG
2.5 V U1 AAL1GATOR-8 PM73123 3 OF 5 PPL_21 PPL_20 PPL_19 PPL_18 PPL_17 PPL_16 PPL_15 PPL_14 PPL_13 PQH_4 PPL_12 PQH_3 PPL_11 PQH_2 PPL_10 PPL_9 PQH_1 PPL_8 PPL_7 PPH_15 PPL_6 PPH_14 PPL_5 PPH_13 PPL_4 PPH_12 PPL_3 PPH_11 PPL_2 PPH_10 PPL_1 PPH_9 PPH_8 PCL_8 PPH_7 PCL_7 PPH_6 PCL_6 PPH_5 PCL_5 PPH_4 PCL_4 PPH_3 PCL_3 PPH_2 PCL_2 PPH_1 PCL_1 PCH_8 PCH_7 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 PQL_4 PQL_3 PQL_2 PQL_1 POWER SUPPLY
Y4 AB2 AA4 AB3 AB5 AA6 W5 Y7 W7 Y9 AA9 AB9 W10 AB7 AB11 W11 AB13 AA13 Y13 W14 AA14 W15 Y19 AA21 A2 W3 B3 A3 C4 B5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AAL1_D<15..0>\I
9D7<>
RN7
1 2 3 4 8 7 6 5 4.7K
3.3 V
3.3 V
A7 C14 M21 U20 W17 AA11 U4 E4 D16 A22 Y18 W4 E1 L1 R4 V2 Y5 W8 W16 AB17 Y20 R21 L19 F20 A18 D11 D4
R91
4.7K
1
TP2
WRB_IN\I RDB_IN\I AAL1_CSB\I AAL1_ACKB\I AAL1_INTB\I TRSTB\I RSTB\I AAL1_SYSCLK\I TCK\I TMS\I TDI\I AAL1_TDOUT
13E5> 13E5> 13E5> 13E5< 13E2< 13G5> 13F5> 8C9> 13G5> 13H5> 13H5> 11E2<
W22 B4 D8 A12 D15 C17 C19 G19 M19 V21 W21 Y17 AB15 AB12 Y11 AB8 AA3 AA2 M4 G4 C3 F1 T2 AA7 Y14 V22 L21 D19 C11 D5 D22 AB21 K3
F
E
U1 RL_SYNC<7..0>\I AAL1GATOR-8 PM73123 1 OF 5 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE TL_SYNC<7..0>\I
D
3G2> 2G2>
3F2> 2F2>
RL_DATA<7..0>\I
3G2> 2G2>
RL_SIG<7..0>\I
C
3G2> 2G2>
RL_CLK<7..0>\I
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
8E2>
C4B\I C4B AND C16B ARE USED IN H-MVIP MODE
B21 C20 F19 J19 M20 P20 U22 W20 D20 E22 H20 K20 N19 R19 T20 AB22 B20 C22 G21 J21 M22 P22 T22 Y21 A21 E21 G22 J22 L22 P21 T21 AA22 D18
RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK
A19 B22 F21 H21 K21 N22 T19 V19 B19 E20 F22 J20 L20 P19 U19 V20 C18 D21 G20 H19 K19 N20 R20 Y22 A20 C21 E19 H22 K22 N21 R22 U21 C16 B18
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 330
8F9>
D
TL_DATA<7..0>\I
2F6< 3F6<
TL_SIG<7..0>\I
2G6< 3G6<
C TL_CLK<7..0>\I
8F9<>
3.3 V C16B\I
4.7K R90 R92
8E2>
LINE INTERFACE
2
B
1
LINE_MODE0 = 'GND' WHEN DIRECT MODE 'HIGH' WHEN H-MVIP MODE HEADER2 J5
DRAWING: AAL1GATOR_8_1.1 AAL1 Thu May 17 11:12:34 2001
B
2.5 V 3.3 V
0.01UF C127 0.01UF C126 0.01UF C125 0.01UF C124 0.01UF C123 0.01UF C122 0.01UF C121 0.01UF C120 0.01UF 0.01UF 0.01UF C118 0.01UF C117 0.01UF C116 0.01UF
C119
C143
C115
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:10 2 1 OF 13 A
A DECOUPLING CAPS ONE CAP PER TWO POWER PINS
TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN AAL1GATOR-8.1 ENGINEER: KM
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
INPUT_D<15..0>
G RX POD J27 RECEPTACLE_RA
1 2 3 4 5 6 7 8 09 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 9 18 10 19 11 20 12 21 13 22 14 23 15 24 25 26 27 0 1 2 3 4 28 29 30 31 32 33 34 35 36 37 38 39 40
G J28 TX POD RECEPTACLE_RA
1 2 3 4 5 6 7 8
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PRTY SOC LENB A0 A1 A2 A3 A4 CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
F
E RN9
1 2 3 4
330
8 7 6 5
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
PBGA U1
V3 15 Y1 14 W1 13 U3 12 U2 11 V4 10 9 T3 8 U1 7 P4 6 N3 5 N2 4 N1 3 N4 2 M3 1 M1 0 L2 4 V1 3 T1 2 R2 1 T4 0 P3 R3 M2 P2 R1 P1
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PRTY SOC LENB A0 A1 A2 A3 A4 CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV RATM_CLK RATM_SOC
AAL1GATOR-8 PM73123 5 OF 5
OUTPUT_D<15..0> TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 TATM_PAR TATM_ENB TATM_CLAV TATM_SOC TATM_CLK
C2 B1 D2 E3 D1 E2 F3 F2 H4 J3 J2 J1 L3 K2 K1 K4 C1 G2 G3 G1 H1 D3 H3 J4 H2 F4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
NOT USED IN ATM MODE RPHY_ADD<4..0> TATM_PAR TATM_ENB TATM_CLAV TATM_SOC TATM_CLK
0 1 2 3 4
28 29 30 31 32 33 34 35 36 37 38 39 40
UTOPIA INTERFACE
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
F
E
RN10 330
1 2 3 4 8 7 6 5
UTOPIA2 INTERFACE
UTOPIA2 INTERFACE
D
D
RATM_ENB RATM_CLAV RATM_CLK TPHY_ADD<4..0> NOT USED IN ATM MODE RATM_SOC RATM_PAR C C
B
DRAWING: AAL1GATOR_8_1.3 AAL1 Thu May 17 11:12:40 2001
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN AAL1GATOR_8.3 ENGINEER: 10 9 8 7 6 5 4 3 KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:12 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G RAM_D<15..0> RAM_PAR1 RAM_PAR0 3.3 V RAM_A<16..0> U1 AAL1GATOR-8 PM73123 4 OF 5 F
16 C10 15 D9 14 A9 13 B9 12 C9 11 D7 10 A8 C8 9 8 B11 B7 7 A6 6 C7 5 B6 4 A5 3 C6 2 A4 1 C5 0 80 50 16 49 15 48 14 47 13 46 12 45 11 44 10 81 9 82 8 99 7 100 6 32 5 33 4 34 3 35 2 36 1 37 0
G
100MHZ U7
VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
91 65 41 15 77 70 61 54 27 20 11 4
RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0
E
RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB RAM INTERFACE
A17 B16 C15 D17 B15 A15 B17 B14 D14 C13 B13 A13 D13 C12 B12 D12 A16 A11 B10 B8 D6 D10 A10 A14
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM_WE0B RAM_WE1B RAM_CSB RAM_OEB RAM_R/WB RAM_CLK\I 3.3 V RN8 1
2 3 4 93 94 92 98 97 86 88 89 87 85 16 66 14 64 31
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> BA BB CE1 CE2 CE3 G W CK CKE ADV PD QE FT ZZ LBO
GS841Z18 (256K X 18)
DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> TDI TDO TMS TCK
74 73 72 69 68 63 62 59 58 24 23 22 19 18 13 12 9 8 39 42 38 43
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
F
AAL1_TDOUT AAL1_TDO\I TMS\I TCK\I
10E5> 2B10< 13H5> 13G5>
E
3.3 V
4.7K 1 R93
8C9>
4.7K
8 7 6 5
TP3
D
90 76 71 67 60 55 40 26 21 17 10 5
VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
D
C
C
B
DRAWING: AAL1GATOR_8_1.2 AAL1 Thu May 17 11:12:37 2001
B
3.3 V
PMC-Sierra, Inc.
0.01UF C131 0.01UF 0.01UF C129 0.01UF C132 C130 C128
0.01UF
0.01UF
C133
A
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN AAL1GATOR-8.2 ENGINEER: KM 2
ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:11 1 OF 13
A
DECOUPLING CAPS
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3 V 3.3 V
REV
DESCRIPTION
DATE
APPR
H
H
4.7K
4.7K
J30 P_1 P_2 P_3 P_4 P_5 P_6
1 2 3 4 5 6 4.7K R76
R75
R77
C144 0.01UF
0.1UF
U10
4 6 5
HCT08
TRSTB\I
2B10< 3A10< 10E5<
C145
JTAG PORT
TMS\I TDI\I TCK\I TDO1\I
2B10< 3A10< 10E5< 11E2< 10E5< 2B10< 3A10< 10E5< 11E2< 3B10>
3.3 V
G 3.3 V SW1
2
PBNO
G
1
1 2
U14 MR SENSE HYST GND
VCC CTL RESET RESET
8 7 6 5
3.3 V
931 R85 1.0K
10K R83
3 4
MAX700
R84 9 16
U10
8 10
RES_ARRAY_15
HCT08
F RN11 4.7K
RSTB\I
2B7<
3A7<
8G9<
10E5<
F D1
1
YELLOW 2 RN6 YELLOW 2
2 1 2 3 4
3.3 V 270
8 7 6 5
COMET-QUADS INTERRUPT LEDS D3 D2
1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
11
12
13
14
15
16
17
18
U4
YELLOW AAL1GATOR-8 INTERRUPT LED
OE2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
U10
12 11 13
HCT08
HCT541
Y0
19 1 330 R5
9
8
7
6
5
4
3
E
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
9D10<>
UP_D<15..0>\I
D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
2
OE1
DEV_SELB\I
A7
A6
A5
A4
A3
A2
A1
A0
9D5<
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
AAL1_ACKB\I AAL1_CSB\I CS2B\I CS3B\I RDB_IN\I WRB_IN\I UP_A<21..0>\I
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 3
E
10E5> 10E5< 9A8< 8G9<
11
U8
12 0 1 4.7K 13 4.7K
AAL1_INTB\I IRQ2_BUS<1..0>\I
10E5> 2B7> 3A7>
9B8< 10E5< 9B8< 10F5< 9D10<
HCT08
VCC
R87 R88
VCC U43 F1
3
2.5 V 2.5V
1 1 C139 1UF 2
D
0.750A
C140 1UF
LT1118CST VIN VOUT TAB GND GND
2 4
SB1 P<1> P<2> P<3> P<4>
?
2 4
270
R78
D8 SUPER_GREEN
GND1
VCC
VCC
3.3 V C
C
4.7K
R81
U42
LT1528 VIN SHDN GND VOUT SENS
1 47UF 47UF 47UF 2 330 R79 47UF
F2
0.47UF
5 4 C138
3.000A
+
1 C137 C136 C135 C134
2
1 270 R82
2
3
VCC1
1 3
VCC SB2 P<1> P<2> P<3> P<4>
?
C142 47UF 2 4 1.0UF
270
D10 SUPER_GREEN
R80
D9 SUPER_GREEN
B
B
DIN96
C141
+
+
CONNECT UNUSED INPUTS TO GND U10
1
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: 1 TITLE: AAL1GATOR_8 COMET_QUAD REF DESIGN MICRO_INTERFACE ENGINEER: KM 2 ISSUE DATE: 00/01/21 REVISION NUMBER: 1.0 PAGE:13 TRUE 1 OF 13 A
A
2
HCT08
3
DRAWING TITLE=MICRO_INTERFACE ABBREV=MICRO LAST_MODIFIED=Thu May 17 11:12:14 2001
10
9
8
7
6
5
4
3
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
47
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE 2
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1991089 (P2) Issue date: June 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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